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SN74ALVCH16501DL

更新时间： 2024-09-14 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 156K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16501DL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.16其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：6.1 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74ALVCH16501DL 数据手册

 浏览型号SN74ALVCH16501DL的Datasheet PDF文件第2页浏览型号SN74ALVCH16501DL的Datasheet PDF文件第3页浏览型号SN74ALVCH16501DL的Datasheet PDF文件第4页浏览型号SN74ALVCH16501DL的Datasheet PDF文件第5页浏览型号SN74ALVCH16501DL的Datasheet PDF文件第6页浏览型号SN74ALVCH16501DL的Datasheet PDF文件第7页 
SN74ALVCH16501  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES024D – JULY 1995 – REVISED MAY 2000  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
2
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
3
4
5
A3  
B3  
6
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
V
7
CC  
CC  
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
8
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8 13  
A9 14  
44 B8  
43 B9  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
V
22  
35  
V
CC  
CC  
A16 23  
34 B16  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLKAB. When OEAB  
is high, the outputs are active. When OEAB is low,  
the outputs are in the high-impedance state.  
A17 24  
33 B17  
GND 25  
A18 26  
32 GND  
31 B18  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16501 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74ALVCH16501DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16501DLR TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
74ALVCH16501DLRG4 TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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