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SN74ALVCH16500DL PDF预览

SN74ALVCH16500DL

更新时间： 2024-11-04 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
11页 157K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16500DL 数据手册

 浏览型号SN74ALVCH16500DL的Datasheet PDF文件第2页浏览型号SN74ALVCH16500DL的Datasheet PDF文件第3页浏览型号SN74ALVCH16500DL的Datasheet PDF文件第4页浏览型号SN74ALVCH16500DL的Datasheet PDF文件第5页浏览型号SN74ALVCH16500DL的Datasheet PDF文件第6页浏览型号SN74ALVCH16500DL的Datasheet PDF文件第7页 
SN74ALVCH16500  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES023G – JULY 1995 – REVISED MAY 2000  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEAB  
LEAB  
A1  
GND  
A2  
1
2
3
4
5
6
7
8
9
56 GND  
55 CLKAB  
54 B1  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
53 GND  
52 B2  
A3  
51 B3  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
50  
V
CC  
A4  
CC  
49 B4  
A5  
48 B5  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A6 10  
47 B6  
GND 11  
A7 12  
46 GND  
45 B7  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8 13  
44 B8  
A9 14  
43 B9  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
V
22  
23  
24  
25  
26  
27  
28  
35  
34  
33  
32  
31  
30  
29  
V
CC  
CC  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
GND  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on  
the  
high-to-low  
transition  
of  
CLKAB.  
Output-enable OEAB is active high. When OEAB  
is high, the B-port outputs are active. When OEAB  
is low, the B-port outputs are in the  
high-impedance state.  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high, and OEBA is active low).  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking/current-sourcing capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16500 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74ALVCH16500DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16500DLR TI

完全替代

 具有三态输出的 18 位通用总线收发器 | DL | 56 | -40 to 85

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