5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVCH16501DGG
SN74ALVCH16501DGG PDF预览

SN74ALVCH16501DGG

更新时间： 2024-11-08 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
11页 156K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ALVCH16501DGG 数据手册

 浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第2页浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第3页浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第4页浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第5页浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第6页浏览型号SN74ALVCH16501DGG的Datasheet PDF文件第7页 
SN74ALVCH16501  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES024D – JULY 1995 – REVISED MAY 2000  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
2
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
3
4
5
A3  
B3  
6
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
V
7
CC  
CC  
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
8
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8 13  
A9 14  
44 B8  
43 B9  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
V
22  
35  
V
CC  
CC  
A16 23  
34 B16  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLKAB. When OEAB  
is high, the outputs are active. When OEAB is low,  
the outputs are in the high-impedance state.  
A17 24  
33 B17  
GND 25  
A18 26  
32 GND  
31 B18  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16501 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

下载PDF

SN74ALVCH16501DGG 替代型号

型号 品牌 替代类型 描述 数据表
IDT74ALVCH16501PA8 IDT

功能相似

 Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,

与SN74ALVCH16501DGG相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVCH16501DGGR TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16501DL TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16501DLR TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16501KR TI

获取价格

 		18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16524 TI

获取价格

 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16524DGG TI

获取价格

 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16524DL TI

获取价格

 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16524DLR TI

获取价格

 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSO
SN74ALVCH16525 TI

获取价格

 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16525DGG TI

获取价格

 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

与SN74ALVCH16501DGG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证