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SN74ALVCH16373

更新时间： 2024-11-17 22:34:43
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德州仪器 - TI 锁存器输出元件
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16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALVCH16373 数据手册

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SN74ALVCH16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCES020C – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
ESD Protection Exceeds 2000 V Per  
MIL-STD-833, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
V
CC  
CC  
1Q5  
1Q6  
1D5  
1D6  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
GND 10  
39 GND  
1Q7  
1Q8  
1D7  
1D8  
11  
12  
38  
37  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
2Q1 13  
2Q2 14  
GND 15  
2Q3 16  
2Q4 17  
36 2D1  
35 2D2  
34 GND  
33 2D3  
32 2D4  
description  
This 16-bit transparent D-type latch is designed  
for 1.65-V to 3.6-V V operation.  
CC  
V
18  
31  
V
CC  
CC  
2Q5 19  
2Q6 20  
GND 21  
2Q7 22  
2Q8 23  
2OE 24  
30 2D5  
29 2D6  
28 GND  
27 2D7  
26 2D8  
25 2LE  
The SN74ALVCH16373 is particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
This device can be used as two 8-bit latches or  
one 16-bit latch. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old  
data can be retained or new data can be entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74ALVCH16373 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC16373 TI

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