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SN74ALVCH16272DLR PDF预览

SN74ALVCH16272DLR

更新时间： 2024-09-15 14:20:27
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路
页数 文件大小 规格书
9页 485K
描述
ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56, PLASTIC, SSOP-56

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SN74ALVCH16272DLR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：18.415 mm逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER
功能数量：12端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74ALVCH16272DLR 数据手册

 浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第2页浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第3页浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第4页浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第5页浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第6页浏览型号SN74ALVCH16272DLR的Datasheet PDF文件第7页 
SN74ALVCH16272  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
D
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
LE1B  
2B3  
OEB  
2
CLKENA2  
2B4  
Bus Hold on Data Inputs Eliminates  
the Need for External Pullup/Pulldown  
Resistors  
3
4
GND  
2B2  
GND  
2B5  
5
D
Packaged in Plastic Shrink Small-Outline  
(DL) and Thin Shrink Small-Outline (DGG)  
Packages  
6
2B1  
2B6  
7
V
V
2B7  
CC  
A1  
CC  
8
9
A2  
2B8  
description  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
A9  
GND  
A10  
A11  
A12  
2B9  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
This 12-bit to 24-bit bus exchanger is designed for  
1.65-V to 3.3-V V operation.  
CC  
The SN74ALVCH16272 is intended for applica-  
tions where two separate datapaths must be  
multiplexed onto, or demultiplexed from, a single  
datapath. This device is particularly suitable as an  
interface between conventional DRAMs and  
high-speed microprocessors.  
1B8  
1B7  
Data from the A inputs is stored in the internal  
registers on the low-to-high transition of the clock  
(CLK) input, when the CLKENA inputs are low. A  
two-stage pipeline is provided in each of the  
A-to-1B and A-to-2B paths to serve as a shallow  
write buffer.  
V
V
CC  
1B1  
CC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
1B2  
GND  
1B3  
LE2B  
SEL  
Transparent latches are provided in the B-to-A  
pathtoallowasynchronousoperationtomaximize  
memory access throughput. These latches  
transfer data when the latch-enable (LE) inputs  
are low. The select (SEL) line selects 1B or 2B  
data for the A outputs. Data flow is controlled by  
the active-low output enables (OEA, OEB).  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16272 is characterized for operation from –40°C to 85°C.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3–75  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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