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SN74ALVCH16280DBBR PDF预览

SN74ALVCH16280DBBR

更新时间： 2024-11-05 21:09:35
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 498K
描述
ALVC/VCX/A SERIES, 16-BIT EXCHANGER, TRUE OUTPUT, PDSO80, TSSOP-80

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SN74ALVCH16280DBBR 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：80
Reach Compliance Code：unknown风险等级：5.84
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G80
长度：17 mm逻辑集成电路类型：BUS EXCHANGER
位数：16功能数量：1
端口数量：3端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

SN74ALVCH16280DBBR 数据手册

 浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第2页浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第3页浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第4页浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第5页浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第6页浏览型号SN74ALVCH16280DBBR的Datasheet PDF文件第7页 
SN74ALVCH16280  
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER  
WITH BYTE MASKS AND 3-STATE OUTPUTS  
SCES033A – JULY 1995 – REVISED FEBRUARY 1999  
DBB PACKAGE  
(TOP VIEW)  
D
D
D
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
V
V
CC  
GND  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
CC  
GND  
2B7  
1B7  
2B6  
GND  
1B6  
2B5  
1B5  
2
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1B8  
2B8  
1B9  
GND  
2B9  
1B10  
2B10  
V
1B11  
2B11  
1B12  
2B12  
GND  
1B13  
2B13  
1B14  
2B14  
3
4
5
D
Packaged in Thin Shrink Small-Outline  
Package  
6
7
8
description  
9
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
CC  
CC  
This 16-bit to 32-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V V operation. This  
2B4  
1B4  
2B3  
1B3  
GND  
2B2  
1B2  
2B1  
1B1  
CC  
device is intended for use in applications where  
data must be transferred from a narrow  
high-speed bus to a wide lower-frequency bus.  
The device provides synchronous data exchange  
between the A and B ports. Data is stored in the  
internal registers on the low-to-high transition of  
the clock (CLK) input. For data transfer in the  
B-to-A direction, SEL selects 1B or 2B data for the  
A outputs.  
V
V
CC  
CC  
GND  
2D2  
1D2  
2D1  
1D1  
GND  
1B15  
2B15  
1B16  
2B16  
For data transfer in the A-to-B direction, a  
two-stage pipeline is provided in the 1B path, and  
a single storage register in the 2B path. Data flow  
is controlled by the active-low output enable (OE)  
and the direction-control (DIR) input. DIR is  
registered to synchronize the bus direction  
changes with the clock.  
V
V
A16  
CC  
C1  
CC  
C2 28  
53 A15  
A1  
GND  
A2  
A3  
A4  
A14  
GND  
A13  
A12  
A11  
29  
30  
31  
32  
33  
34  
52  
51  
50  
49  
48  
47  
Two mask bits are provided for both data bytes.  
The D outputs arecontrolledbytheactive-lowOE.  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
V
V
CC  
CC  
A5 35  
A6  
A7 37  
46 A10  
A9  
45  
36  
44 A8  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
GND 38  
CLK 39  
SEL 40  
43 GND  
42 OE  
41 DIR  
The SN74ALVCH16280 is characterized for  
operation from –40°C to 85°C.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3–85  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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