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SN74ALVCH162820

更新时间： 2024-11-04 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 128K
描述
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS

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SN74ALVCH162820 数据手册

 浏览型号SN74ALVCH162820的Datasheet PDF文件第2页浏览型号SN74ALVCH162820的Datasheet PDF文件第3页浏览型号SN74ALVCH162820的Datasheet PDF文件第4页浏览型号SN74ALVCH162820的Datasheet PDF文件第5页浏览型号SN74ALVCH162820的Datasheet PDF文件第6页浏览型号SN74ALVCH162820的Datasheet PDF文件第7页 
SN74ALVCH162820  
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS  
AND 3-STATE OUTPUTS  
SCES012G – JULY 1995 – REVISED NOVEMBER 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OE  
1Q1  
1Q2  
GND  
2Q1  
2Q2  
CLK  
D1  
NC  
GND  
D2  
NC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
3
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
V
V
7
CC  
CC  
3Q1  
3Q2  
4Q1  
GND  
4Q2  
5Q1  
5Q2  
6Q1  
6Q2  
7Q1  
GND  
7Q2  
8Q1  
8Q2  
D3  
NC  
D4  
GND  
NC  
D5  
NC  
D6  
NC  
D7  
GND  
NC  
D8  
8
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For tape and reel order entry:  
The DGGR package is abbreviated to GR.  
description  
NC  
This 10-bit flip-flop is designed for 1.65-V to 3.6-V  
V
V
CC  
CC  
V
operation.  
CC  
9Q1  
9Q2  
GND  
10Q1  
10Q2  
2OE  
D9  
NC  
GND  
D10  
NC  
The  
SN74ALVCH162820  
flip-flops  
are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock (CLK) input, the device  
provides true data at the Q outputs.  
NC  
A buffered output-enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
NC – No internal connection  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74ALVCH162820_15 TI

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SN74ALVCH162820DGG TI

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 		ALVC/VCX/A SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74ALVCH162827 TI

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SN74ALVCH162827_08 TI

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SN74ALVCH162827DGG TI

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 		20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74ALVCH162827DGGR TI

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 		20-Bit Buffer/Driver With 3-State Outputs 56-TSSOP -40 to 85

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