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SN74ALVCH16282

更新时间： 2024-09-14 23:09:43
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德州仪器 - TI 输出元件
页数 文件大小 规格书
10页 143K
描述
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16282 数据手册

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SN74ALVCH16282  
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES036D – JULY 1995 – REVISED MARCH 2000  
DBB PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
80  
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41  
V
V
CC  
CC  
2
GND  
2B9  
1B9  
2B8  
GND  
1B8  
2B7  
1B7  
GND  
1B10  
2B10  
1B11  
GND  
2B11  
1B12  
2B12  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-up Performance Exceeds 250 mA Per  
JESD 17  
6
7
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
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18  
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35  
36  
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38  
39  
40  
V
V
CC  
CC  
2B6  
1B6  
2B5  
1B5  
GND  
2B4  
1B4  
2B3  
1B3  
1B13  
2B13  
1B14  
2B14  
GND  
1B15  
2B15  
1B16  
2B16  
Packaged in Thin Very Small-Outline  
Package  
NOTE: For tape and reel order entry:  
The DBBR package is abbreviated to GR.  
description  
The SN74ALVCH16282 is an 18-bit to 36-bit  
registered bus exchanger designed for 1.65-V to  
3.6-V V  
operation.  
CC  
V
V
CC  
CC  
GND  
2B2  
1B2  
2B1  
1B1  
GND  
1B17  
2B17  
1B18  
2B18  
This device is intended for use in applications in  
which data must be transferred from a narrow  
high-speed bus to a wide lower-frequency bus. It  
is designed specifically for low-voltage (3.3-V)  
V
operation.  
CC  
V
V
CC  
A1  
CC  
The device provides synchronous data exchange  
between the two ports. Data is stored in the  
internal registers on the low-to-high transition of  
the clock (CLK) input. For data transfer in the  
B-to-A direction, the select (SEL) input selects 1B  
or 2B data for the A outputs.  
A18  
A17  
A16  
GND  
A15  
A14  
A13  
A2  
A3  
GND  
A4  
A5  
A6  
For data transfer in the A-to-B direction, a  
two-stage pipeline is provided in the 1B path, with  
a single storage register in the 2B path. Data flow  
is controlled by the active-low output enable (OE)  
and the DIR input. The DIR control pin is  
registered to synchronize the bus direction  
changes with the clock.  
V
V
CC  
A7  
CC  
A12  
A11  
A10  
GND  
OE  
A8  
A9  
GND  
CLK  
SEL  
DIR  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
The SN74ALVCH16282 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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