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SN65DSI83_V01 PDF预览

SN65DSI83_V01

更新时间: 2024-11-07 02:51:27
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德州仪器 - TI /
页数 文件大小 规格书
49页 2823K
描述
SN65DSI83 MIPI® DSI Bridge to FlatLink™ LVDS Single-Channel DSI to Single-Link LVDS Bridge

SN65DSI83_V01 数据手册

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SN65DSI83
SLLSEC1I – SEPTEMBER 2012 – REVISED OCTOBER 2020  
SN65DSI83 MIPI® DSI Bridge to FlatLink™ LVDS  
Single-Channel DSI to Single-Link LVDS Bridge  
1 Features  
3 Description  
Implements MIPI® D-PHY version 1.00.00 physical  
The SN65DSI83 DSI to FlatLink bridge device  
layer front-end and display serial interface (DSI)  
version 1.02.00  
Single channel DSI receiver configurable for 1, 2,  
3, or 4 D-PHY data lanes per channel operating up  
to 1 Gbps/lane  
Supports 18 bpp and 24 bpp DSI video packets  
with RGB666 and RGB888 formats  
Max resolution up to 60 fps WUXGA  
1920 × 1200 at 18 bpp and 24 bpp color with  
reduced blanking. suitable for 60 fps 1366 × 768 /  
1280 × 800 at 18 bpp and 24 bpp  
FlatLinkoutput for single-link LVDS  
Supports single channel DSI to single-link LVDS  
operating mode  
features a single-channel MIPI D-PHY receiver front-  
end configuration with four lanes per channel  
operating at 1 Gbps per lane; a maximum input  
bandwidth of 4 Gbps. The bridge decodes MIPI DSI  
18 bpp RGB666 and 24 bpp RGB888 packets and  
converts the formatted video data stream to a  
FlatLink-compatible LVDS output operating at pixel  
clocks operating from 25 MHz to 154 MHz, offering a  
Single-Link LVDS with four data lanes per link.  
The SN65DSI83 device can support up to WUXGA  
1920 × 1200 at 60 frames per second, at 24 bpp with  
reduced blanking. The SN65DSI83 device is also  
suitable for applications using 60 fps 1366 × 768 /  
1280 × 800 at 18 bpp and 24 bpp. Partial line  
buffering is implemented to accommodate the data  
stream mismatch between the DSI and LVDS  
interfaces.  
LVDS Output Clock Range of 25 MHz to 154 MHz  
LVDS pixel clock may be sourced from free-  
running continuous D-PHY clock or external  
reference clock (REFCLK)  
Designed  
with  
industry-compliant  
interface  
1.8-V main VCC power supply  
technology, the SN65DSI83 device is compatible with  
a wide range of microprocessors, and is designed  
with a range of power management features including  
low-swing LVDS outputs, and the MIPI defined ultra-  
low power state (ULPS) support.  
Low power features include shutdown mode,  
reduced LVDS output voltage swing, common  
mode, and MIPI ultra-low power state (ULPS)  
support  
LVDS channel swap, LVDS PIN order reverse  
feature for ease of PCB routing  
ESD rating ±2 kV (HBM)  
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)  
Temperature range: –40°C to 85°C  
The SN65DSI83 device is implemented in a small  
outline 5-mm × 5-mm nFBGA at 0.5-mm pitch  
package, and operates across a temperature range  
from –40°C to 85°C.  
Device Information (1)  
PART  
NUMBER  
2 Applications  
PACKAGE  
BODY SIZE  
PC & notebooks  
Tablets  
Connected peripherals & printers  
SN65DSI83  
nFBGA (64)  
5.00 mm × 5.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Typical Application  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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