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SN65DSI85ZQER

更新时间： 2024-11-24 12:00:31

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
45页	1114K
描述
MIPI DSI BRIDGE TO FLATLINK LVDS Dual Channel DSI to Dual-Link LVDS Bridge

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SN65DSI85ZQER 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	VFBGA,
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.93
数据速率：	1000 Mbps	JESD-30 代码：	S-PBGA-B64
JESD-609代码：	e1	长度：	5 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
座面最大高度：	1 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	0.5 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm	Base Number Matches：	1

SN65DSI85ZQER 数据手册

SN65DSI85

www.ti.com

SLLSEB9C –SEPTEMBER 2012–REVISED DECEMBER 2012

MIPI® DSI BRIDGE TO FLATLINK™ LVDS

Dual Channel DSI to Dual-Link LVDS Bridge

Check for Samples: SN65DSI85

FEATURES

•

Implements MIPI^®® D-PHY Version 1.00.00

MHz in Dual-Link or Single-Link Mode

234

Physical Layer Front-End and Display Serial

Interface (DSI) Version 1.02.00

•

LVDS Pixel Clock May be Sourced from Free-

Running Continuous D-PHY Clock or External

Reference Clock (REFCLK)

•

Dual Channel DSI Receiver Configurable for

One, Two, Three, or Four D-PHY Data Lanes

Per Channel Operating up to 1 Gbps Per Lane

•

1.8 V Main V_CCPower Supply

Low Power Features Include SHUTDOWN

Mode, Reduced LVDS Output Voltage Swing,

Common Mode, and MIPI® Ultra-Low Power

State (ULPS) Support

•

Supports 18 bpp and 24 bpp DSI Video

Packets with RGB666 and RGB888 Formats

Suitable for 60 fps WQXGA 2560 x 1600

Resolution at 18 bpp and 24 bpp Color, and

WUXGA 1920 x 1200 Resolution with 3D

Graphics at 60 fps (120 fps Equivalent)

•

LVDS Channel SWAP, LVDS PIN Order

Reverse Feature for Ease of PCB Routing

•

ESD Rating ±2 kV (HBM)

•

MIPI® Front-End Configurable for Single-

Channel or Dual-Channel DSI Configurations

Packaged in 64-pin 5x5mm PBGA (ZQE)

Temperature Range: -40°C to 85°C

FlatLink™ Output Configurable for Single-Link

or Dual-Link LVDS

APPLICATIONS

Supports Dual Channel DSI ODD or EVEN and

LEFT or RIGHT Operating Modes

•

Tablet PC, Notebook PC, Netbooks

Mobile Internet Devices

Supports two Single Channel DSI to two

Single-Link LVDS Operating Mode

LVDS Output Clock Range of 25 MHz to 154

DESCRIPTION

The SN65DSI85 DSI to FlatLink™ bridge features a dual-channel MIPI® D-PHY receiver front-end configuration

with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge

decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream

to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a

Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560x1600) at 60 frames per second, as well as 3D Graphics at

WUXGA and True HD (1920 x1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line

buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-

processors, and is designed with a range of power management features including low-swing LVDS outputs, and

the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5x5mm PBGA at 0.5 mm pitch package, and operates across

a temperature range from -40ºC to 85ºC.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

MIPI is a registered trademark of Arasan Chip Systems, Inc.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

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与SN65DSI85ZQER相关器件

型号	品牌	获取价格	描述	数据表
SN65DSI85ZQET	TI	获取价格	IC SPECIALTY TELECOM CIRCUIT, Telecom IC:Other
SN65DSI85ZXHR	TI	获取价格	双通道 MIPI® DSI 转双链路 FlatLink™ LVDS 桥接器 \| ZXH \|
SN65DSI86	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65DSI86IPAPQ1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP \| PAP \| 64 \| -40 to 85
SN65DSI86IPAPRQ1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP \| PAP \| 64 \| -40 to 85
SN65DSI86-Q1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP
SN65DSI86ZQER	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65DSI86ZXHR	TI	获取价格	双通道 MIPI® DSI 转嵌入式 DisplayPort™ (eDP) 桥接器 \| Z
SN65DSI96	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65DSI96ZQER	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)

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