Datasheet > SN65DSI86

SN65DSI86

更新时间： 2024-11-27 12:14:59

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
68页	990K
描述
Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)

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SN65DSI86 数据手册

SN65DSI86

SN65DSI96

www.ti.com

SLLSEH2 –SEPTEMBER 2013

MIPI® DSI BRIDGE to eDP

Check for Samples: SN65DSI86 , SN65DSI96

FEATURES

APPLICATIONS

234

•

Embedded DisplayPort (eDP) 1.4 Compliant

Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR),

2.7Gbps (HBR), or 5.4Gbps (HBR2).

•

Tablet PC, Notebook PC, Netbooks

Mobile Internet Devices

•

Implements MIPI^®D-PHY Version 1.1 Physical

Layer Front-End and Display Serial Interface

(DSI) Version 1.02.00

LCD

eDP TCON

•

Dual Channel DSI Receiver Configurable for

One, Two, Three, or Four D-PHY Data Lanes

Per Channel Operating up to 1.5Gbps Per Lane

DSI86/96

Dual/Single DSI to

eDP

•

Supports 18 bpp and 24 bpp DSI Video

Packets with RGB666 and RGB888 Formats

Suitable for 60fps 4K 4096x2304 Resolution at

18bpp Color, and WUXGA 1920x1200

Resolution with 3D Graphics at 60fps (120fps

Equivalent)

DSI–enabled

Chipset

•

MIPI^®Front-End Configurable for Single-

Channel or Dual-Channel DSI Configuration

Supports Dual Channel DSI ODD/EVEN and

LEFT/RIGHT Operating Modes

DESCRIPTION

The SN65DSI86/96 DSI to embedded DisplayPort

(eDP) bridge features a dual-channel MIPI® D-PHY

receiver front-end configuration with 4 lanes per

channel operating at 1.5Gbps per lane; a maximum

input bandwidth of 12Gbps. The bridge decodes

MIPI® DSI 18bpp RGB666 and 24bpp RGB888

packets and converts the formatted video data stream

to a DisplayPort with up to four lanes at either

1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps,

4.32Gbps, or 5.4Gbps.

1.2V Main VCC Power Supply and 1.8V supply

for Digital I/Os

Low Power Features Include Panel Refresh

and MIPI® Ultra-Low Power State (ULPS)

Support

•

DisplayPort Lane Polarity and assignment

configurable.

Supports 12MHz, 19.2MHz, 26MHz, 27MHz, and

38.4MHz REFCLK

The SN65DSI86/96 is well suited for WQXGA at 60

frames per second, as well as 3D Graphics at 4K and

True HD (1920x1080) resolutions at an equivalent

120fps with up to 24 bits-per-pixel. Partial line

buffering is implemented to accommodate the data

stream mismatch between the DSI and DisplayPort

interfaces.

Adaptive content management and backlight

PWM control enabling optimal user viewing

experience in both low and bright ambient

light environments available in SN65DSI96.

•

ESD Rating ±4 kV (HBM)

Packaged in 64-pin 5x5mm PBGA (ZQE)

Temperature Range: –40°C to 85°C

Integrated into the SN65DSI96 is an adaptive content

management and backlight PWM control called

Assertive Display^®. The purpose of the Assertive

Display^®core is to optimize the viewing experience

on a multimedia display as a function of viewing

environment. It provides coherent management of the

multimedia viewing experience from total darkness to

bright ambient light conditions enabling the display to

operate at reduced power and in bright sunshine.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Assertive Display is a registered trademark of Apical.

MIPI is a registered trademark of Arasan Chip Systems, Inc.

MIPI is a registered trademark of MIPI Alliance, Inc.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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与SN65DSI86相关器件

型号	品牌	获取价格	描述	数据表
SN65DSI86IPAPQ1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP \| PAP \| 64 \| -40 to 85
SN65DSI86IPAPRQ1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP \| PAP \| 64 \| -40 to 85
SN65DSI86-Q1	TI	获取价格	汽车类 MIPI® DSI 桥接转 eDP
SN65DSI86ZQER	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65DSI86ZXHR	TI	获取价格	双通道 MIPI® DSI 转嵌入式 DisplayPort™ (eDP) 桥接器 \| Z
SN65DSI96	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65DSI96ZQER	TI	获取价格	Embedded DisplayPort (eDP) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR)
SN65EL11	TI	获取价格	5-V PECL/ECL 1:2 Fanout Buffer
SN65EL11D	TI	获取价格	5-V PECL/ECL 1:2 Fanout Buffer
SN65EL11DGK	TI	获取价格	5-V PECL/ECL 1:2 Fanout Buffer

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