SN65ELT22
www.ti.com ............................................................................................................................................................................................ SLLS924–DECEMBER 2008
5-V Dual TTL-to-Differential PECL Translator
1
FEATURES
PIN ASSIGNMENT
•
1.1-ns (max) Propagation Delay
Operating Range: VCC = 4.2V to 5.7V with
GND = 0 V
•
D or DGK PACKAGE
(TOP VIEW)
•
•
•
< 50-ps (typ) Output-to-Output Skew
Built-In Temperature Compensation
V
1
2
8
7
Q
Q
CC
0
Drop-In Compatible to the MC10ELT22,
MC100ELT22
D
D
0
1
0
APPLICATIONS
•
•
Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data
6
5
3
4
Q
1
DESCRIPTION
GND
Q
1
The SN65ELT22 is a dual TTL-to-differential PECL
translator. It operates on +5-V supply and ground
only. The output is undetermined when the inputs are
left floating. The low output skew makes the device
an ideal solution for clock or data signal translation.
Table 1. Pin Descriptions
PIN
FUNCTION
TTL inputs
The SN65ELT22 is housed in an industry standard
SOIC-8 package and is also available in an optional
TSSOP-8 package.
D0, D1
Q0, Q0, Q1, Q1
VCC
PECL outputs
Positive supply
Ground
GND
ORDERING INFORMATION(1)
PART NUMBER
SN65ELT22D
PART MARKING
PACKAGE
LEAD FINISH
SN65ELT22
SN65ELT22
SOIC
NiPdAu
NiPdAu
SN65ELT22DGK
SOIC-TSSOP
(1) Leaded device options are not initially available; contact a sales representative for further details
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.