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SN65EPT23DR PDF预览

SN65EPT23DR

更新时间: 2024-11-27 06:12:51
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 253K
描述
3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

SN65EPT23DR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:GREEN, PLASTIC, MS-012AA, SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.22Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:606740
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOIC127P600X175-8N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
系列:65EP输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:4.9 mm负载电容(CL):20 pF
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:1功能数量:2
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260Prop。Delay @ Nom-Sup:1.9 ns
传播延迟(tpd):1.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.11 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
最小 fmax:300 MHzBase Number Matches:1

SN65EPT23DR 数据手册

 浏览型号SN65EPT23DR的Datasheet PDF文件第2页浏览型号SN65EPT23DR的Datasheet PDF文件第3页浏览型号SN65EPT23DR的Datasheet PDF文件第4页浏览型号SN65EPT23DR的Datasheet PDF文件第5页浏览型号SN65EPT23DR的Datasheet PDF文件第6页浏览型号SN65EPT23DR的Datasheet PDF文件第7页 
SN65EPT23  
www.ti.com  
SLLS969 NOVEMBER 2009  
3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator  
Check for Samples: SN65EPT23  
1
FEATURES  
PINOUT ASSIGNMENT  
Dual 3.3 V Differential LVPECL/LVDS to  
LVTTL/LVCMOS Buffer Translator  
+
+
24 mA LVTTL Ouputs  
VCC  
Q0  
1
2
8
7
D0  
D0  
Operating Range  
+
VCC = 3.0 V to 3.6 V  
GND = 0 V  
LVTTL  
LVPECL  
+
Support for Clock Frequencies > 300 MHz  
2.0 ns Typical Propagation Delay  
6
5
Q1  
3
4
D1  
D1  
Built-in Temperature Compensation  
Drop in Compatible to MC100EPT23  
+
GND  
APPLICATIONS  
Data and Clock Transmission Over Backplane  
Signaling Level Conversion for Clock or Data  
Table 1. PIN DESCRIPTION  
PIN  
FUNCTION  
Q0, Q1  
LVTTL/LVCMOS Outputs  
DESCRIPTION  
D0, D 0, D1, D 1  
Differential LVPECL/LVDS/CML Inputs  
Positive Supply  
The SN65EPT23 is a low power dual LVPECL/LVDS  
to LVTTL/LVCMOS translator device. The device  
includes circuitry to maintain inputs at Vcc/2 when left  
open. The SN65EPT23 is housed in an industry  
standard SOIC-8 package and is also available in  
TSSOP-8 option.  
VCC  
GND  
EP  
Ground  
Exposed pad must be connected to a  
sufficient thermal conduit. Electrically  
connect to the most negative supply or  
leave floating open.  
ORDERING INFORMATION(1)  
PART NUMBER  
SN65EPT23D/DR  
PART MARKING  
PACKAGE  
LEAD FINISH  
NiPdAu  
EPT23  
SSTI  
SOIC  
SN65EPT23DGK/DGKR  
MSOP  
NiPdAu  
(1) Leaded device option not initially available; contact TI sales representative for further information.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65EPT23DR 替代型号

型号 品牌 替代类型 描述 数据表
SN65EPT23DGKR TI

完全替代

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
SN65EPT23DGK TI

完全替代

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
SN65EPT23D TI

完全替代

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

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