Datasheet > SN65EPT23_10

SN65EPT23_10

更新时间： 2024-09-13 11:50:11

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
12页	395K
描述
3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

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SN65EPT23_10 数据手册

SN65EPT23

www.ti.com

SLLS969 –NOVEMBER 2009

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

Check for Samples: SN65EPT23

FEATURES

PINOUT ASSIGNMENT

•

Dual 3.3 V Differential LVPECL/LVDS to

LVTTL/LVCMOS Buffer Translator

•

24 mA LVTTL Ouputs

V_CC

Operating Range

–

V_CC= 3.0 V to 3.6 V

GND = 0 V

LVTTL

LVPECL

•

Support for Clock Frequencies > 300 MHz

2.0 ns Typical Propagation Delay

Built-in Temperature Compensation

Drop in Compatible to MC100EPT23

GND

APPLICATIONS

•

Data and Clock Transmission Over Backplane

Signaling Level Conversion for Clock or Data

Table 1. PIN DESCRIPTION

FUNCTION

Q₀, Q₁

LVTTL/LVCMOS Outputs

DESCRIPTION

D₀, D ₀, D₁, D ₁

Differential LVPECL/LVDS/CML Inputs

Positive Supply

The SN65EPT23 is a low power dual LVPECL/LVDS

to LVTTL/LVCMOS translator device. The device

includes circuitry to maintain inputs at Vcc/2 when left

open. The SN65EPT23 is housed in an industry

standard SOIC-8 package and is also available in

TSSOP-8 option.

V_CC

GND

Ground

Exposed pad must be connected to a

sufficient thermal conduit. Electrically

connect to the most negative supply or

leave floating open.

ORDERING INFORMATION⁽¹⁾

PART NUMBER

SN65EPT23D/DR

PART MARKING

PACKAGE

LEAD FINISH

NiPdAu

EPT23

SSTI

SOIC

SN65EPT23DGK/DGKR

MSOP

NiPdAu

(1) Leaded device option not initially available; contact TI sales representative for further information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

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