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SN65EPT21D PDF预览

SN65EPT21D

更新时间: 2024-11-24 11:49:39
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器转换器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 384K
描述
3.3-V Differential PECL/LVDS to TTL Translator

SN65EPT21D 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.78
系列:65EP输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:4.9 mm负载电容(CL):20 pF
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260Prop。Delay @ Nom-Sup:1.9 ns
传播延迟(tpd):1.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
最小 fmax:300 MHzBase Number Matches:1

SN65EPT21D 数据手册

 浏览型号SN65EPT21D的Datasheet PDF文件第2页浏览型号SN65EPT21D的Datasheet PDF文件第3页浏览型号SN65EPT21D的Datasheet PDF文件第4页浏览型号SN65EPT21D的Datasheet PDF文件第5页浏览型号SN65EPT21D的Datasheet PDF文件第6页浏览型号SN65EPT21D的Datasheet PDF文件第7页 
SN65EPT21  
www.ti.com  
SLLS970 NOVEMBER 2009  
3.3-V Differential PECL/LVDS to TTL Translator  
Check for Samples: SN65EPT21  
1
FEATURES  
PIN ASSIGNMENT(Add pullup on BOTH  
inputs)  
1 ns Propagation Delay  
Fmax > 300MHz  
Operating Range: VCC = 3.0 V to 3.6 V with  
GND = 0 V  
D or DGK PACKAGE  
(TOP VIEW)  
24-mA TTL Output  
+
Built-In Temperature Compensation  
VCC  
1
2
8
7
NC  
+
Drop-In Compatible to the MC10EPT21,  
MC100EPT21  
LVTTL  
Q
D
+
APPLICATIONS  
Data and Clock Transmission Over Backplane  
Signaling Level Conversion for Clock or Data  
6
5
NC  
3
4
D
LVPECL  
VBB  
GND  
DESCRIPTION  
The SN65EPT21 is  
a differential PECL-to-TTL  
translator. It operates on +3.3 V supply and ground  
only. The device includes circuitry to maintain inputs  
at Vcc/2 when left open.  
Table 1. Pin Descriptions  
PIN  
FUNCTION  
The VBB pin is a reference voltage output for the  
device. When the device is used in single-ended  
mode, the unused input should be tied to VBB. This  
reference voltage can also be used to bias the input  
when it is ac coupled. When it is used, place a  
Q
LVTTL/LVCMOS Output  
D, D  
VCC  
VBB  
GND  
NC  
Differential LVPECL/LVDS/CML Input  
Positive Supply  
Output Reference Voltage  
Ground  
0.01μF decoupling capacitor between VCC and VBB  
.
Also limit the sink/source current to < 0.5 mA to VBB  
Leave VBB open when it is not used.  
.
No Connect  
EP  
(DFN8 only) Thermal exposed pad must be  
connected to a sufficient thermal conduit.  
Electrically connect to the most negative supply  
(GND) or leave unconnected, floating open.  
The SN65EPT21 is housed in an industry standard  
SOIC-8 package and is also available in an optional  
TSSOP-8 package.  
ORDERING INFORMATION(1)  
PART NUMBER  
SN65EPT21D/DR  
PART MARKING  
PACKAGE  
LEAD FINISH  
NiPdAu  
EPT21  
SSSI  
SOIC  
SN65EPT21DGK/DGKR  
MSOP  
NiPdAu  
(1) Leaded device options are not initially available; contact a sales representative for further details.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65EPT21D 替代型号

型号 品牌 替代类型 描述 数据表
SN65EPT21DR TI

完全替代

3.3-V Differential PECL/LVDS to TTL Translator
MC100EPT21DG ONSEMI

类似代替

3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

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