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SN65DSI85ZXHR PDF预览

SN65DSI85ZXHR

更新时间: 2024-11-07 11:06:47
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页数 文件大小 规格书
45页 1114K
描述
双通道 MIPI® DSI 转双链路 FlatLink™ LVDS 桥接器 | ZXH | 64 | -40 to 85

SN65DSI85ZXHR 数据手册

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SN65DSI85  
www.ti.com  
SLLSEB9C SEPTEMBER 2012REVISED DECEMBER 2012  
MIPI® DSI BRIDGE TO FLATLINK™ LVDS  
Dual Channel DSI to Dual-Link LVDS Bridge  
Check for Samples: SN65DSI85  
1
FEATURES  
Implements MIPI®® D-PHY Version 1.00.00  
MHz in Dual-Link or Single-Link Mode  
234  
Physical Layer Front-End and Display Serial  
Interface (DSI) Version 1.02.00  
LVDS Pixel Clock May be Sourced from Free-  
Running Continuous D-PHY Clock or External  
Reference Clock (REFCLK)  
Dual Channel DSI Receiver Configurable for  
One, Two, Three, or Four D-PHY Data Lanes  
Per Channel Operating up to 1 Gbps Per Lane  
1.8 V Main VCC Power Supply  
Low Power Features Include SHUTDOWN  
Mode, Reduced LVDS Output Voltage Swing,  
Common Mode, and MIPI® Ultra-Low Power  
State (ULPS) Support  
Supports 18 bpp and 24 bpp DSI Video  
Packets with RGB666 and RGB888 Formats  
Suitable for 60 fps WQXGA 2560 x 1600  
Resolution at 18 bpp and 24 bpp Color, and  
WUXGA 1920 x 1200 Resolution with 3D  
Graphics at 60 fps (120 fps Equivalent)  
LVDS Channel SWAP, LVDS PIN Order  
Reverse Feature for Ease of PCB Routing  
ESD Rating ±2 kV (HBM)  
MIPI® Front-End Configurable for Single-  
Channel or Dual-Channel DSI Configurations  
Packaged in 64-pin 5x5mm PBGA (ZQE)  
Temperature Range: -40°C to 85°C  
FlatLink™ Output Configurable for Single-Link  
or Dual-Link LVDS  
APPLICATIONS  
Supports Dual Channel DSI ODD or EVEN and  
LEFT or RIGHT Operating Modes  
Tablet PC, Notebook PC, Netbooks  
Mobile Internet Devices  
Supports two Single Channel DSI to two  
Single-Link LVDS Operating Mode  
LVDS Output Clock Range of 25 MHz to 154  
DESCRIPTION  
The SN65DSI85 DSI to FlatLink™ bridge features a dual-channel MIPI® D-PHY receiver front-end configuration  
with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge  
decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream  
to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a  
Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.  
The SN65DSI85 is well suited for WQXGA (2560x1600) at 60 frames per second, as well as 3D Graphics at  
WUXGA and True HD (1920 x1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line  
buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.  
Designed with industry compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-  
processors, and is designed with a range of power management features including low-swing LVDS outputs, and  
the MIPI® defined ultra-low power state (ULPS) support.  
The SN65DSI85 is implemented in a small outline 5x5mm PBGA at 0.5 mm pitch package, and operates across  
a temperature range from -40ºC to 85ºC.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
FlatLink is a trademark of Texas Instruments.  
MIPI is a registered trademark of Arasan Chip Systems, Inc.  
All other trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2012, Texas Instruments Incorporated  

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