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SN65DSI84_V01 PDF预览

SN65DSI84_V01

更新时间: 2024-11-07 02:51:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
50页 2302K
描述
SN65DSI84 MIPI® DSI Bridge To FLATLINK™ LVDS Single Channel DSI to Dual-Link LVDS Bridge

SN65DSI84_V01 数据手册

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SN65DSI84
SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020  
SN65DSI84 MIPI® DSI Bridge To FLATLINK™ LVDS  
Single Channel DSI to Dual-Link LVDS Bridge  
1 Features  
3 Description  
Implements MIPI® D-PHY version 1.00.00 physical  
The SN65DSI84 DSI to FlatLink™ bridge features a  
layer front-end and display serial interface (DSI)  
version 1.02.00  
Single channel DSI receiver configurable for one,  
two, three, or four D-PHY data lanes per channel  
operating up to 1 Gbps per lane  
Supports 18 bpp and 24-bpp DSI video packets  
with RGB666 and RGB888 formats  
Suitable for 60-fps WUXGA 1920 × 1200  
resolution at 18-bpp and 24-bpp color, 60 fps 1366  
× 768 at 18 bpp and 24 bpp  
single-channel MIPI® D-PHY receiver front-end  
configuration with 4 lanes per channel operating at 1  
Gbps per lane; a maximum input bandwidth of 4  
Gbps. The bridge decodes MIPI® DSI 18bpp RGB666  
and 24 bpp RGB888 packets and converts the  
formatted video data stream to  
a
FlatLink™  
compatible LVDS output operating at pixel clocks  
operating from 25 MHz to 154 MHz, offering a Dual-  
Link LVDS, Single-Link LVDS interface with four data  
lanes per link.  
FlatLinkoutput configurable for single-link or  
dual-link LVDS  
Supports single channel DSI to dual-link LVDS  
operating mode  
LVDS output clock range of 25 MHz to 154 MHz in  
dual-link or single-link modes  
LVDS pixel clock may be sourced from free-  
running continuous D-PHY clock or external  
reference clock (REFCLK)  
The SN65DSI84 is well suited for WUXGA 1920 x  
1200 at 60 frames per second, with up to 24 bits-per-  
pixel. Partial line buffering is implemented to  
accommodate the data stream mismatch between the  
DSI and LVDS interfaces.  
Designed  
with  
industry  
compliant  
interface  
technology, the SN65DSI84 is compatible with a wide  
range of micro-processors, and is designed with a  
range of power management features including low-  
swing LVDS outputs, and the MIPI® defined ultra-low  
power state (ULPS) support.  
1.8-V main VCC power supply  
Low power features include shutdown mode,  
reduced LVDS output voltage swing, common  
mode, and MIPI ultra-low power state (ULPS)  
support  
LVDS channel swap, LVDS PIN order reverse  
feature for ease of PCB routing  
ESD rating ±2 kV (HBM)  
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)  
Temperature range: –40°C to 85°C  
The SN65DSI84 is implemented in a small outline  
5x5mm nFBGA at 0.5 mm pitch package, and  
operates across a temperature range from -40°C to  
85°C.  
Device Information (1)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
SN65DSI84  
nFBGA (64)  
5.00 mm × 5.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
2 Applications  
PC & notebooks  
Tablets  
Connected peripherals & printers  
Typical Application  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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