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SN65DSI83ZQER

更新时间： 2024-11-06 12:00:31
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德州仪器 - TI /
页数 文件大小 规格书
34页 1052K
描述
MIPI DSI BRIDGE TO FLATLINK LVDS Single Channel DSI to Single-Link LVDS Bridge

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SN65DSI83ZQER 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：BGA-64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.99Samacsys Description：Single-channel MIPI? DSI to single-link LVDS bridge & FlatLink? integrated circuit
数据速率：1000 MbpsJESD-30 代码：S-PBGA-B64
JESD-609代码：e1长度：5 mm
湿度敏感等级：3功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：SQUARE
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
座面最大高度：1 mm标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

SN65DSI83ZQER 数据手册

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SN65DSI83  
www.ti.com  
SLLSEC1D –SEPTEMBER 2012–REVISED DECEMBER 2012  
MIPI® DSI BRIDGE TO FLATLINK™ LVDS  
Single Channel DSI to Single-Link LVDS Bridge  
Check for Samples: SN65DSI83  
1
FEATURES  
•
Implements MIPI® D-PHY Version 1.00.00  
Reference Clock (REFCLK)  
1.8 V Main VCC Power Supply  
234  
Physical Layer Front-End and Display Serial  
Interface (DSI) Version 1.02.00  
•
•
Low Power Features Include SHUTDOWN  
Mode, Reduced LVDS Output Voltage Swing,  
Common Mode, and MIPI® Ultra-Low Power  
State (ULPS) Support  
•
Single Channel DSI Receiver Configurable for  
One, Two, Three, or Four D-PHY Data Lanes  
Per Channel Operating up to 1 Gbps Per Lane  
•
•
Supports 18 bpp and 24 bpp DSI Video  
Packets with RGB666 and RGB888 Formats  
•
LVDS Channel SWAP, LVDS PIN Order  
Reverse Feature for Ease of PCB Routing  
Max Resolution up to 60 fps WUXGA 1920 x  
1200 at 18 bpp and 24 bpp Color with Reduced  
Blanking. Suitable for 60 fps 1366 x 768 / 1280  
x 800 at 18 bpp and 24 bpp  
•
•
•
ESD Rating ±2 kV (HBM)  
Packaged in 64-pin 5x5mm PBGA (ZQE)  
Temperature Range: -40°C to 85°C  
•
•
FlatLink™ Output for Single-Link LVDS  
APPLICATIONS  
Supports Single Channel DSI to Single-Link  
LVDS Operating Mode  
•
•
Tablet PC, Notebook PC, Netbooks  
Mobile Internet Devices  
•
•
LVDS Output Clock Range of 25 MHz to 154  
MHz  
LVDS Pixel Clock May be Sourced from Free-  
Running Continuous D-PHY Clock or External  
DESCRIPTION  
The SN65DSI83 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end  
configuration with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 4 Gbps. The  
bridge decodes MIPI® DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data  
stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz,  
offering a Single-Link LVDS with four data lanes per link.  
The SN65DSI83 can support up to WUXGA 1920 x 1200 at 60 frames per second, at 24 bpp with reduced  
blanking. It is also suitable for applications using 60 fps 1366 x 768 / 1280 x 800 at 18 bpp and 24 bpp. Partial  
line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.  
Designed with industry compliant interface technology, the SN65DSI83 is compatible with a wide range of micro-  
processors, and is designed with a range of power management features including low-swing LVDS outputs, and  
the MIPI® defined ultra-low power state (ULPS) support.  
The SN65DSI83 is implemented in a small outline 5x5mm PBGA at 0.5 mm pitch package, and operates across  
a temperature range from -40ºC to 85ºC.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
FlatLink is a trademark of Texas Instruments.  
MIPI is a registered trademark of Arasan Chip Systems, Inc.  
All other trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2012, Texas Instruments Incorporated  
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