Datasheet > SN54LVC573A_10

SN54LVC573A_10

更新时间： 2024-11-04 09:17:39

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
28页	1057K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54LVC573A_10 数据手册

SN54LVC573A, SN74LVC573A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

www.ti.com

SCAS300R–JANUARY 1993–REVISED SEPTEMBER 2005

FEATURES

•

Operate From 1.65 V to 3.6 V

Inputs Accept Voltages to 5.5 V

Max t_pdof 6.9 ns at 3.3 V

•

I_offSupports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical V_OLP(Output Ground Bounce) <0.8 V

at V_CC= 3.3 V, T_A= 25°C

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

•

Typical V_OHV(Output V_OHUndershoot) >2 V at

V_CC= 3.3 V, T_A= 25°C

Support Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With 3.3-V

– 1000-V Charged-Device Model (C101)

xxxxx

V_CC

)

SN54LVC573A . . . J OR W PACKAGE

SN74LVC573A . . . DB, DGV, DW, N,

NS, OR PW PACKAGE

SN74LVC573A . . . RGY PACKAGE

(TOP VIEW)

SN54LVC573A . . . FK PACKAGE

(TOP VIEW)

1 20 19

14 6Q

10 11 12 13

13 7Q

GND

DESCRIPTION/ORDERING INFORMATION

The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CCoperation, and the

SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V V_CCoperation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q

outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the

outputs, preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

12 3 4 5 6 7...28

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与SN54LVC573A_10相关器件

型号	品牌	获取价格	描述	数据表
SN54LVC573AFK	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AFKR	TI	获取价格	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SN54LVC573AJ	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AW	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AWR	TI	获取价格	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, FP-20
SN54LVC574	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A_10	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AFK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AJ	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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