5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> SN54LVC74AJ
SN54LVC74AJ PDF预览

SN54LVC74AJ

更新时间： 2024-11-24 22:16:19
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
9页 132K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

SN54LVC74AJ 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.49系列：LVC/LCX/Z
JESD-30 代码：R-GDIP-T14长度：19.56 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
位数：1功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：6 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.7 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：100 MHzBase Number Matches：1

SN54LVC74AJ 数据手册

 浏览型号SN54LVC74AJ的Datasheet PDF文件第2页浏览型号SN54LVC74AJ的Datasheet PDF文件第3页浏览型号SN54LVC74AJ的Datasheet PDF文件第4页浏览型号SN54LVC74AJ的Datasheet PDF文件第5页浏览型号SN54LVC74AJ的Datasheet PDF文件第6页浏览型号SN54LVC74AJ的Datasheet PDF文件第7页 
SN54LVC74A, SN74LVC74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS287H – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC74A . . . J OR W PACKAGE  
SN74LVC74A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1CLK  
1PRE  
1Q  
2CLK  
10 2PRE  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
9
8
1Q  
2Q  
2Q  
CC  
A
GND  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
SN54LVC74A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and DIPs (J)  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
4
5
6
7
8
17  
16  
15  
14  
NC  
description  
1PRE  
NC  
2CLK  
NC  
The SN54LVC74A dual positive-edge-triggered  
D-type flip-flop is designed for 2.7-V to 3.6-V V  
1Q  
2PRE  
CC  
9 10 11 12 13  
operation and the SN74LVC74A dual positive-  
edge-triggered D-type flip-flop is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
NC – No internal connection  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs, regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVC74A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN54LVC74AJ相关器件

型号 品牌 获取价格 描述 数据表
SN54LVC74A-SP TI

获取价格

 		具有清零和预置端的双路正边沿触发式 D 型触发器
SN54LVC74AW TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC86A TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LVC86AFK TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LVC86AFKR TI

获取价格

 		LVC/LCX/Z SERIES, QUAD 2-INPUT XOR GATE, CQCC20, LCC-20
SN54LVC86AJ TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LVC86AW TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LVC86AWR TI

获取价格

 		LVC/LCX/Z SERIES, QUAD 2-INPUT XOR GATE, CDFP14, CERAMIC, FP-14
SN54LVCH244A TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVCH244A_07 TI

获取价格

 		OCTAL BUFFERS/DRIVERS OCTAL BUFFERS/DRIVERS

与SN54LVC74AJ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证