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SN54LVT125FK PDF预览

SN54LVT125FK

更新时间： 2024-02-05 05:48:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件输入元件信息通信管理
页数 文件大小 规格书
7页 119K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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SN54LVT125FK 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP14,.3针数：14
Reach Compliance Code：unknown风险等级：5.84
其他特性：TYP VOLP < 0.8V @ VCC = 3.3V, TA = 25 DEG C; INPUTS CAN BE DRIVEN BY 3.3/5V DEVICES; BUS HOLD INPUTS控制类型：ENABLE LOW
系列：LVTJESD-30 代码：R-GDIP-T14
长度：19.56 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.048 A
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：3.3 V
最大电源电流（ICC）：7 mAProp。Delay @ Nom-Sup：4.2 ns
传播延迟（tpd）：5.1 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm

SN54LVT125FK 数据手册

 浏览型号SN54LVT125FK的Datasheet PDF文件第2页浏览型号SN54LVT125FK的Datasheet PDF文件第3页浏览型号SN54LVT125FK的Datasheet PDF文件第4页浏览型号SN54LVT125FK的Datasheet PDF文件第5页浏览型号SN54LVT125FK的Datasheet PDF文件第6页浏览型号SN54LVT125FK的Datasheet PDF文件第7页 
SN54LVT125, SN74LVT125  
3.3-V ABT QUADRUPLE BUS BUFFERS  
WITH 3-STATE OUTPUTS  
SCBS133D – MAY 1992 – REVISED JULY 1995  
SN54LVT125 . . . J PACKAGE  
SN74LVT125 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
4A  
4Y  
3OE  
3A  
3Y  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
8
GND  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
SN54LVT125 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
3
2
1
20 19  
18 4A  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
1Y  
NC  
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
Support Live Insertion  
2OE  
NC  
NC  
3OE  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
2A  
9 10 11 12 13  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (J) DIPs  
NC – No internal connection  
description  
These bus buffers are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The ′LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state  
when the associated output-enable (OE) input is high.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT125 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT125 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVT125 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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