Datasheet > SN54LVC652A_15

SN54LVC652A_15

更新时间： 2024-11-26 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
13页	198K
描述
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54LVC652A_15 数据手册

SN54LVC652A, SN74LVC652A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCAS303H – JANUARY 1993 – REVISED AUGUST 1998

SN74LVC652A . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

CLKAB

SAB

OEAB

= 3.3 V, T = 25°C

CLKBA

SBA

OEBA

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic

GND 12

13 B8

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW)

Packages, and Ceramic Chip Carriers (FK)

SN54LVC652A . . . FK PACKAGE

(TOP VIEW)

description

The SN54LVC652A octal bus transceiver and

operation, and the SN74LVC652A octal bus

transceiver and register is designed for 1.65-V to

28 27 26

OEBA

3.6-V V

operation.

These devices consist of bus transceiver circuits,

D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the

data bus or from the internal storage registers.

A5 10

A6 11

12 13 14 15 16 17 18

Output-enable (OEAB and OEBA) inputs are

provided to control the transceiver functions.

Select-control (SAB and SBA) inputs are provided

to select whether real-time or stored data is

transferred. The circuitry used for select control

eliminates the typical decoding glitch that occurs

NC – No internal connection

in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and

a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that are

performed with the ’LVC652A.

Data on the A or B data bus, or both, is stored in the internal D-type flip-flops by low-to-high transitions at the

appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and

SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by

simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other

data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

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与SN54LVC652A_15相关器件

型号	品牌	获取价格	描述	数据表
SN54LVC652AFK	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC74	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74A	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74A_07	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74A_10	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74AFK	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74AJ	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74A-SP	TI	获取价格	具有清零和预置端的双路正边沿触发式 D 型触发器
SN54LVC74AW	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC86A	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

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