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SN54LVC74

更新时间： 2024-09-28 22:16:19
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德州仪器 - TI 触发器
页数 文件大小 规格书
9页 132K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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SN54LVC74 数据手册

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SN54LVC74A, SN74LVC74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS287H – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC74A . . . J OR W PACKAGE  
SN74LVC74A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1CLK  
1PRE  
1Q  
2CLK  
10 2PRE  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
9
8
1Q  
2Q  
2Q  
CC  
A
GND  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
SN54LVC74A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and DIPs (J)  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
4
5
6
7
8
17  
16  
15  
14  
NC  
description  
1PRE  
NC  
2CLK  
NC  
The SN54LVC74A dual positive-edge-triggered  
D-type flip-flop is designed for 2.7-V to 3.6-V V  
1Q  
2PRE  
CC  
9 10 11 12 13  
operation and the SN74LVC74A dual positive-  
edge-triggered D-type flip-flop is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
NC – No internal connection  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs, regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVC74A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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