Datasheet > SN54LVC574A_10

SN54LVC574A_10

更新时间： 2024-02-20 06:05:33

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
30页	1169K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54LVC574A_10 数据手册

SN54LVC574A, SN74LVC574A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

Operate From 1.65 V to 3.6 V

Inputs Accept Voltages to 5.5 V

Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

Specified From −40°C to 85°C,

−40°C to 125°C, and −55°C to 125°C

off

Supports Partial-Power-Down Mode

Operation

Max t of 7 ns at 3.3 V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical V

(Output Ground Bounce)

OLP

<0.8 V at V = 3.3 V, T = 25°C

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

Typical V

(Output V Undershoot)

OHV

>2 V at V = 3.3 V, T = 25°C

− 1000-V Charged-Device Model (C101)

SN54LVC574A . . . FK PACKAGE

SN54LVC574A . . . J OR W PACKAGE

SN74LVC574A . . . DB, DGV, DW, N, NS,

OR PW PACKAGE

SN74LVC574A . . . RGY PACKAGE

(TOP VIEW)

2 1 20 19

V_CC

18 2Q

17 3Q

16 4Q

18 2Q

CLK

9 10 11 12 13

GND

description/ordering information

The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V operation, and the

SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I . The I circuitry disables the

off

outputs, preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

unless otherwise noted. On all other products, production

testing of all parameters.

processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...30

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与SN54LVC574A_10相关器件

型号	品牌	获取价格	描述	数据表
SN54LVC574AFK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AJ	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AW	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC646A	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC646AFK	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC646A-SP	TI	获取价格	RAD-TOLERANT CLASS V OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN54LVC652A	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC652A_15	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC652AFK	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC74	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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