Datasheet > 逻辑 > 总线驱动器/收发器> SN54LVC573AWR

SN54LVC573AWR

更新时间： 2024-11-04 13:13:47

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
9页	130K
描述
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, FP-20

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SN54LVC573AWR 技术参数

生命周期：	Obsolete	零件包装代码：	DFP
包装说明：	DFP,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.56	系列：	LVC/LCX/Z
JESD-30 代码：	R-CDFP-F20	长度：	13.09 mm
逻辑集成电路类型：	BUS DRIVER	位数：	8
功能数量：	1	端口数量：	2
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	传播延迟（tpd）：	8.4 ns
认证状态：	Not Qualified	座面最大高度：	2.54 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	2.7 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	6.92 mm
Base Number Matches：	1

SN54LVC573AWR 数据手册

SN54LVC573A, SN74LVC573A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCAS300I – JANUARY 1993 – REVISED JUNE 1998

SN54LVC573A . . . J OR W PACKAGE

SN74LVC573A . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

Power Off Disables Outputs, Permitting

Live Insertion

13 7Q

12 8Q

11 LE

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

GND 10

SN54LVC573A . . . FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

Ceramic Flat (W) Packages, Ceramic Chip

Carriers (FK), and DIPs (J)

1 20 19

description

9 10 11 12 13

TheSN54LVC573AoctaltransparentD-typelatch

is designed for 2.7-V to 3.6-V V operation and

the SN74LVC573A octal transparent D-type latch

is designed for 1.65-V to 3.6-V V operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN54LVC573AWR相关器件

型号	品牌	获取价格	描述	数据表
SN54LVC574	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A_10	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AFK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AJ	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AW	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC646A	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC646AFK	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVC646A-SP	TI	获取价格	RAD-TOLERANT CLASS V OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN54LVC652A	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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