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SN54AC374_07 PDF预览

SN54AC374_07

更新时间: 2024-11-25 04:51:23
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德州仪器 - TI 触发器
页数 文件大小 规格书
18页 684K
描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SN54AC374_07 数据手册

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ꢉ ꢅꢊꢄꢋ ꢌꢍꢊ ꢎꢏ ꢐ ꢐꢌ ꢑꢐ ꢍꢊꢒ ꢓꢑ ꢑꢐ ꢒꢐꢌ ꢔ ꢋꢓ ꢏ ꢍꢔ ꢋꢉ ꢏ  
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003  
SN54AC374 . . . J OR W PACKAGE  
SN74AC374 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9.5 ns at 5 V  
pd  
3-State Noninverting Outputs Drive Bus  
Lines Directly  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
19 8Q  
1
2
3
4
5
6
7
8
9
10  
20  
18 8D  
D
Full Parallel Access for Loading  
17  
16  
15  
14  
13  
12  
11  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
description/ordering information  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54AC374 . . . FK PACKAGE  
(TOP VIEW)  
The eight flip-flops of the ’AC374 devices are  
D-type edge-triggered flip-flops. On the positive  
transition of the clock (CLK) input, the Q outputs  
are set to the logic levels set up at the data (D)  
inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
4
5
6
7
8
17  
16  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
the increased drive provide the capability to drive  
bus lines in bus-organized systems without need  
for interface or pullup components.  
15 6Q  
14 6D  
9 10 11 12 13  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC374N  
SN74AC374N  
Tube  
SN74AC374DW  
SN74AC374DWR  
SN74AC374NSR  
SN74AC374DBR  
SN74AC374PW  
SN74AC374PWR  
SNJ54AC374J  
SOIC − DW  
AC374  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC374  
AC374  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC374  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC374J  
SNJ54AC374W  
SNJ54AC374FK  
Tube  
SNJ54AC374W  
SNJ54AC374FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢓ ꢋꢍ ꢏꢒ ꢔ ꢍꢆꢯꢂ ꢆꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢉ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
ꢛꢡ  
ꢛꢟ  
ꢙꢡ  
ꢧꢣ  
ꢝꢣ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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