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SN54AC533

更新时间: 2024-11-05 22:59:11
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德州仪器 - TI 锁存器输出元件
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6页 123K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AC533 数据手册

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SN54AC533, SN74AC533  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS555A – NOVEMBER 1995 – REVISED MAY 1996  
SN54AC533 . . . J OR W PACKAGE  
SN74AC533 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
3-State Inverting Outputs Drive Bus Lines  
Directly  
Full Parallel Access for Loading  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
description  
GND  
The ’AC533 are octal transparent D-type latches  
with 3-state outputs. When the latch-enable (LE)  
SN54AC533 . . . FK PACKAGE  
(TOP VIEW)  
input is high, the  
Q outputs follow the  
complements of the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the inverse  
logic levels set up at the D inputs.  
3
2 1 20 19  
18  
8D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or a high-  
impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
17 7D  
16  
7Q  
15  
6Q  
14  
6D  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54AC533 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AC533 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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