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SMJ4C1024FQ PDF预览

SMJ4C1024FQ

更新时间： 2024-01-20 16:34:07
品牌 Logo 应用领域
德州仪器 - TI 存储
页数 文件大小 规格书
27页 414K
描述
1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY

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SMJ4C1024FQ 数据手册

 浏览型号SMJ4C1024FQ的Datasheet PDF文件第2页浏览型号SMJ4C1024FQ的Datasheet PDF文件第3页浏览型号SMJ4C1024FQ的Datasheet PDF文件第4页浏览型号SMJ4C1024FQ的Datasheet PDF文件第5页浏览型号SMJ4C1024FQ的Datasheet PDF文件第6页浏览型号SMJ4C1024FQ的Datasheet PDF文件第7页 
SMJ4C1024  
1048576 BY 1-BIT  
DYNAMIC RANDOM-ACCESS MEMORY  
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996  
HJ PACKAGE  
(TOP VIEW)  
JD PACKAGE  
(TOP VIEW)  
Organization . . . 1048576 × 1-Bit  
Processed to MIL-STD-883, Class B  
Single 5-V Supply (10% Tolerance)  
D
W
RAS  
TF  
1
2
3
4
5
20  
19  
18  
17  
16  
V
SS  
Q
CAS  
NC  
A9  
D
W
RAS  
TF  
A0  
A1  
V
SS  
Q
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
Performance Ranges:  
CAS  
A9  
A8  
A7  
A6  
A5  
A4  
ACCESS ACCESS ACCESS  
READ  
OR  
WRITE  
CYCLE  
(MIN)  
TIME  
TIME  
TIME  
NC  
t
t
t
a(R)  
a(C)  
a(CA)  
(t  
(t  
RAC  
)
(t  
CAC  
)
)
AA  
(MAX)  
(MAX)  
(MAX)  
A2  
A3  
A0  
A1  
A2  
A3  
6
15  
14  
13  
12  
11  
A8  
A7  
A6  
A5  
A4  
’4C1024-80  
’4C1024-10  
’4C1024-12  
’4C1024-15  
80 ns  
100 ns  
120 ns  
150 ns  
20 ns  
25 ns  
30 ns  
40 ns  
40 ns  
45 ns  
55 ns  
70 ns  
150 ns  
190 ns  
220 ns  
260 ns  
7
V
CC  
8
9
Enhanced Page-Mode Operation for Faster  
Memory Access  
– Higher Data Bandwidth Than  
Conventional Page Mode Parts  
– Random Single-Bit Access Within a Row  
With a Column Address  
V
10  
CC  
HK PACKAGE  
(TOP VIEW)  
V
D
W
RAS  
TF  
NC  
A0  
A1  
A2  
A3  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
SS  
Q
2
CAS  
NC  
A9  
A8  
A7  
A6  
A5  
A4  
3
One of TI’s CMOS Megabit Dynamic  
Random-Access Memory (DRAM) Family  
Including SMJ44C256 — 256K × 4  
Enhanced Page Mode  
4
5
6
7
CAS-Before-RAS (CBR) Refresh  
8
9
Long Refresh Period  
V
10  
CC  
512-Cycle Refresh in 8 ms (Max)  
3-State Unlatched Output  
Low Power Dissipation  
FQ/HL PACKAGES  
(TOP VIEW)  
SV PACKAGE  
(SIDE VIEW)  
A9  
Q
D
RAS  
NC  
A0  
D
W
RAS  
TF  
10 11  
V
SS  
Q
CAS  
NC  
A9  
1
All Inputs/Outputs and Clocks Are  
TTL-Compatible  
CAS  
2
4
9
8
7
6
12  
13  
14  
15  
3
V
SS  
5
Packaging Offered:  
– 20/26-Pin J-Leaded Ceramic Surface  
Mount Package (HJ Suffix)  
– 18-Pin 300-Mil Ceramic Dual-In-Line  
Package (JD Suffix)  
– 20-Pin Ceramic Flatpack (HK Suffix)  
– 20/26-Terminal Leadless Ceramic  
Surface Mount Package (FQ/HL Suffixes)  
– 20-Pin Ceramic Zig-Zag In-Line Package  
(SV Suffix)  
W
6
7
TF  
NC  
A1  
A3  
A4  
A6  
A8  
8
NC  
9
10  
12  
14  
16  
18  
20  
11  
13  
15  
17  
19  
A2  
V
CC  
A5  
A7  
A0  
A1  
A2  
A3  
5
4
3
2
1
16  
17  
18  
19  
20  
A8  
A7  
A6  
A5  
A4  
V
CC  
Operating Temperature Range  
– 55°C to 125°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...27

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