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SI5325B-B-GM PDF预览

SI5325B-B-GM

更新时间: 2024-11-23 03:57:03
品牌 Logo 应用领域
芯科 - SILICON 时钟
页数 文件大小 规格书
14页 228K
描述
UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

SI5325B-B-GM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN,
针数:36Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.79
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N36
长度:6 mm功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.9 mm
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:6 mmBase Number Matches:1

SI5325B-B-GM 数据手册

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Si5325  
PRELIMINARY DATA SHEET  
µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER  
Description  
Features  
The Si5325 is a low jitter, precision clock multiplier for Generates any frequency from 10 to 945 MHz and  
applications requiring clock multiplication without jitter  
attenuation. The Si5325 accepts dual clock inputs ranging  
from 10 to 710 MHz and generates two clock outputs ranging  
from 10 to 945 MHz and select frequencies to 1.4 GHz. The  
two outputs are divided down separately from a common  
source. The device provides virtually any frequency  
translation combination across this operating range. The  
Si5325 input clock frequency and clock multiplication ratio  
are programmable through an I2C or SPI interface. The  
Si5325 is based on Silicon Laboratories' 3rd-generation  
DSPLL® technology, which provides any-rate frequency  
synthesis in a highly integrated PLL solution that eliminates  
the need for external VCXO and loop filter components. The  
select frequencies to 1.4 GHz from an input  
frequency of 10 to 710 MHz  
Low jitter clock outputs w/jitter generation as low as  
0.6 ps rms (30 kHz–1.3 MHz)  
Integrated loop filter with selectable loop bandwidth  
(150 kHz to 2 MHz)  
Dual clock inputs w/manual or automatically  
controlled hitless switching  
Dual clock outputs with selectable signal format  
(LVPECL, LVDS, CML, CMOS)  
Support for ITU G.709 and custom FEC ratios  
(255/238, 255/237, 255/236)  
DSPLL loop bandwidth is digitally programmable, providing LOS, FOS alarm outputs  
jitter performance optimization at the application level.  
Digitally-controlled output phase adjust  
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325  
is ideal for providing clock multiplication in high performance  
timing applications.  
2
I C or SPI programmable  
On-chip voltage regulator for 1.8, 2.5, or 3.3 V  
±10% operation  
Applications  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
SONET/SDH OC-48/OC-192 line cards  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 and custom FEC line cards  
Optical modules  
Wireless basestations  
Data converter clocking  
xDSL  
SONET/SDH + PDH clock synthesis  
Test and measurement  
÷ N31  
÷ N32  
CKIN1  
CKIN2  
÷ NC1  
÷ NC2  
CKOUT1  
CKOUT2  
®
DSPLL  
÷ N2  
VDD (1.8, 2.5, or 3.3 V)  
GND  
Control  
Alarms  
Signal Detect  
I2C/SPI Port  
Clock Select  
Device Interrupt  
Preliminary Rev. 0.26 7/07  
Copyright © 2007 by Silicon Laboratories  
Si5325  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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