PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
ProductDescription
Product Features
Pericom Semiconductors PI74AVC+ series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed.
PI74AVC+16652 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
The PI74AVC+16652 is a 16-bit bus transceiver and register
designedforlow1.65V to3.6VVCC operation.Itconsistsof D-type
flip-flopsandcontrolcircuitryarrangedformultiplexedtransmission
of data directly from the data bus or from the internal storage
registers. The device can be used as two 8-bit transceivers or one
16-bittransceiver.
I
supports partial power-down operation
OFF
3.6V I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
dataistransferred.Alowinputlevelselectsreal-timedata,andahigh
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Industrial operation: 40°C to +85°C
Available Packages:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
LogicBlockDiagram
56
Data on the A or B bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock (CLKAB
or CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA.Inthisconfiguration,eachoutputreinforcesitsinput.Thus,
when all other data sources to the two sets of bus lines are in the
high-impedance state, each set of bus lines remains at its last level
configuration.
1OEBA
1
1OEAB
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V through a pull-up resistor and
CC
OEAB should be tied to GND through a pull-down resistor; the
minimumvalue of the resistor is determined by the current-sinking
current sourcing capability of the driver.
TO SEVEN OTHER CHANNELS
29
2OEBA
28
2OEAB
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
TO SEVEN OTHER CHANNELS
PS8550
07/31/01
1