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PI74AVC+16823K PDF预览

PI74AVC+16823K

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
其他 - ETC 触发器
页数 文件大小 规格书
10页 151K
描述
18-Bit D-Type Flip-Flop

PI74AVC+16823K 数据手册

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PI74AVC+16823  
2.5V 18-Bit Bus Interface  
Flip-Flop with 3-State Outputs  
Product Features  
ProductDescription  
+
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Pericom Semiconductor’s PI74AVC series of logic circuits are  
PI74AVC 16823 is designed for low voltage operation,  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
V
= 1.65V to 3.6V  
CC  
True ±24mA Balanced Drive @ 3.3V  
I supports partial power-down operation  
+
The18-bitPI74AVC 16823bus-interfaceflip-flop isdesignedfor  
OFF  
1.65V to 3.6V V operation. It features 3-state outputs designed  
CC  
3.6V I/O Tolerant Inputs and Outputs  
specificallyfordrivinghighlycapacitiveorrelativelylow-impedance  
loads. This device is particularly suitable for implementing wider  
bufferregisters,I/Oports,bidirectionalbusdriverswithparity,and  
workingregisters.  
• All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
Thedevicecanbeusedastwo9-bitflip-flopsorone18-bitflip-flop.  
WiththeClockEnable(CLKEN)inputLOW,theD-typeflip-flops  
enter data on the low-to-high transitions of the clock. Taking  
CLKEN HIGH disables the clock buffer, thus latching the outputs.  
TakingtheClear(CLR)inputLOWcausestheQoutputstogoLOW  
independently of the clock.  
• Industrial operation at –40°C to +85°C  
• Available Packages:  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 173 mil wide plastic TVSOP (K)  
LogicBlockDiagram  
A buffered Output Enable (OE) input can be used to place the nine  
outputs in either a normal logic state (high or low logic levels) or  
high-impedance state. In the high-impedance state, the outputs  
neither load n or drive the bus lines significantly. The high-  
impedancestateandincreaseddriveprovidethecapabilitytodrive  
bus lines without need for interface or pullup components.  
2
1OE  
1
1CLR  
55  
CE  
R
1CLKEN  
TheOutputEnable(OE)inputdoesnotaffecttheinternaloperation  
oftheflip-flops.Olddatacanberetainedornewdatacanbeentered  
while the outputs are in the high-impedance state.  
56  
54  
3
C1  
1D  
1
CLK  
1Q1  
1D1  
To ensure the high-impedance state during power up or power  
down, OE should be tied to V through a pullup resistor; the  
CC  
minimumvalueoftheresistorisdeterminedbythecurrent-sinking  
capability of the driver.  
8
27  
2OE  
28  
30  
2
CLR  
2
CLKEN  
CE  
R
C1  
15  
29  
42  
2CLK  
2Q1  
2D1  
1D  
8
PS8489  
07/24/00  
1

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