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PI74AVC+16841K PDF预览

PI74AVC+16841K

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
其他 - ETC 锁存器
页数 文件大小 规格书
10页 535K
描述
10-Bit D-Type Latch

PI74AVC+16841K 数据手册

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PI74AVC+16841  
2.5V 20-Bit Bus Interface D-Type  
Latch with 3-State Outputs  
Product Features  
ProductDescription  
• PI74AVC+16841 is designed for low-voltage operation,  
Pericom Semiconductor’s PI74AVC+ series of logic circuits are  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
VCC = 1.65V to 3.6V  
• True ±24mA Balanced Drive @ 3.3V  
• IOFF supports partial power-down operation  
• 3.6V I/O Tolerant Inputs and Outputs  
ThePI74AVC+16841,a20-bitbus-interfaceD-typelatch, isdesigned  
for1.65Vto3.6VV operation.  
CC  
The device features 3-state outputs designed specifically for  
driving highly capacitive or relatively low-impedance loads.  
It is particularly suitable for implementing buffer registers,  
unidirectional bus drivers, and working registers.  
• All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
• Industrial operation: –40°C to +85°C  
• Available Packages:  
The device can be used as two 10-bit latches or one  
20-bitlatch(transparentD-type).ThedevicehasnoninvertingData  
(D) inputs and provides true data at its outputs. While the Latch  
Enable(1LEor2LE)inputisHIGH,theQoutputsofthecorresponding  
10-bit latch follow the D inputs. When LE is taken LOW, the Q  
outputs are latched at the levels set up at the D inputs.  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 173 mil wide plastic TVSOP (K)  
LogicBlockDiagram  
A buffered Output Enable (1OE or 2OE) input can be used to place  
theoutputsofthecorresponding10-bitlatchineitheranormallogic  
state (high or low logic levels) or a high-impedance state. In that  
state, outputs neither load nor drive the bus lines significantly.  
1
1OE  
56  
1LE  
C1  
TheOutputEnable(OE)inputdoesnotaffecttheinternaloperation  
of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
2
1Q1  
55  
1D1  
1D  
To ensure the high-impedance state during power up or power  
down, OE should be tied to V through a pullup resistor; the  
CC  
minimumvalue of the resistor is determined by the current-sinking  
capability of the driver.  
TO NINE OTHER CHANNELS  
28  
29  
2OE  
2LE  
C1  
1D  
15  
2Q1  
42  
2D1  
TO NINE OTHER CHANNELS  
PS8549  
07/31/01  
1

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