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PI74AVC16244K PDF预览

PI74AVC16244K

更新时间: 2024-10-28 06:03:11
品牌 Logo 应用领域
百利通 - PERICOM 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 527K
描述
2.5V 16-Bit Buffer Driver with 3-State Outputs

PI74AVC16244K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP48,.25,16
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
控制类型:ENABLE LOW系列:AVC
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:9.7 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:3 ns传播延迟(tpd):3.7 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

PI74AVC16244K 数据手册

 浏览型号PI74AVC16244K的Datasheet PDF文件第2页浏览型号PI74AVC16244K的Datasheet PDF文件第3页浏览型号PI74AVC16244K的Datasheet PDF文件第4页浏览型号PI74AVC16244K的Datasheet PDF文件第5页浏览型号PI74AVC16244K的Datasheet PDF文件第6页浏览型号PI74AVC16244K的Datasheet PDF文件第7页 
PI74AVC+16244  
2.5V 16-Bit Buffer Driver  
with 3-State Outputs  
Product Features  
ProductDescription  
• PI74AVC+16244 is designed for low-voltage operation,  
VCC = 1.65V to 3.6V  
Pericom Semiconductor’s PI74AVC+ series of logic circuits are  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
• True ±24mA Balanced Drive @ 3.3V  
PI74AVC+16244 is a noninverting 16-bit buffer/driver designed  
• Compatible with Philips and T.I.AVC Logic family  
• IOFF supports partial power-down operation  
• 3.6V I/O Tolerant inputs and outputs  
forlow-voltage1.65Vto3.6VV operation.  
CC  
The buffer/driver is designed specifically to improve both the  
performance and density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and transmitters.  
• All outputs contain a patented DDC  
(Dynamic Drive Control) circuit that reduces noise without  
degrading propagation delay  
The device can be used as four 4-bit buffers, two 8-bit buffers, or  
one 16-bit buffer. It provides inverting outputs and symmetrical  
active-low output-enable (OE) inputs.  
• Industrial operation: –40°C to +85°C  
• Available Packages:  
– 48-pin 240-mil wide plastic TSSOP  
– 48-pin 173-mil wide plastic TVSOP  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor in which  
the minimum value is determined by the current-sinking capability  
of the driver.  
LogicBlockDiagram  
1
25  
1OE  
3OE  
47  
46  
2
3
36  
35  
13  
14  
1A1  
1A2  
1A3  
1A4  
1Y1  
1Y2  
1Y3  
1Y4  
3A1  
3A2  
3A3  
3A4  
3Y1  
3Y2  
3Y3  
3Y4  
44  
43  
5
6
33  
32  
16  
17  
24  
30  
48  
41  
2OE  
2A1  
4OE  
4A1  
19  
20  
8
9
2Y1  
2Y2  
2Y3  
2Y4  
4Y1  
4Y2  
4Y3  
4Y4  
29  
27  
26  
40  
38  
37  
2A2  
2A3  
2A4  
4A2  
4A3  
4A4  
22  
23  
11  
12  
PS8507A  
12/07/01  
1

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