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PI74AVC+16820KEX PDF预览

PI74AVC+16820KEX

更新时间: 2024-10-28 20:06:31
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路电视
页数 文件大小 规格书
10页 521K
描述
Bus Driver, AVC Series, 1-Func, 10-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56

PI74AVC+16820KEX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
系列:AVCJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:11.3 mm
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):4 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

PI74AVC+16820KEX 数据手册

 浏览型号PI74AVC+16820KEX的Datasheet PDF文件第2页浏览型号PI74AVC+16820KEX的Datasheet PDF文件第3页浏览型号PI74AVC+16820KEX的Datasheet PDF文件第4页浏览型号PI74AVC+16820KEX的Datasheet PDF文件第5页浏览型号PI74AVC+16820KEX的Datasheet PDF文件第6页浏览型号PI74AVC+16820KEX的Datasheet PDF文件第7页 
PI74AVC+16820  
2.5V 10-Bit Flip-Flop with  
Dual and 3-State Outputs  
Product Features  
ProductDescription  
• PI74AVC+16820 is designed for low-voltage operation,  
VCC = 1.65V to 3.6V  
Pericom Semiconductor’s PI74AVC+ series of logic circuits are  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
• True ±24mA Balanced Drive @ 3.3V  
• IOFF supports partial power-down operation  
• 3.6V I/O Tolerant inputs and outputs  
ThePI74AVC+16820,a10-bitflip-flopdesignedfor1.65Vto3.6V  
V
CC  
operation, is designed with edge-triggered D-type flip-flops.  
Onthepositivetransitionofclock(CLK)input,thedeviceprovides  
true data at the Q outputs.  
• All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
A buffered output-enable (OE) input can be used to place the ten  
outputsineitheranormallogicstate(HIGHorLOWlevel)orahigh-  
impedance state. In the high-impedance state, the outputs neither  
loadnordrivethebuslinessignificantly.Thehigh-impedancestate  
and increased drive provide the capacity to drive bus lines without  
the need for interface or pullup components.  
• Industrial operation: –40°C to +85°C  
• Available Packages:  
– 56-pin 240-mil wide plastic TSSOP  
– 56-pin 173-mil wide plastic TVSOP  
OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
PinConfiguration  
To ensure the high-impedance state during power up or power  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CLK  
D1  
1OE  
1Q1  
1Q2  
GND  
2Q1  
2Q2  
VCC  
3Q1  
3Q2  
4Q1  
GND  
4Q2  
5Q1  
5Q2  
6Q1  
6Q2  
7Q1  
GND  
7Q2  
8Q1  
8Q2  
VCC  
9Q1  
9Q2  
GND  
10Q1  
10Q2  
2OE  
down, OE should be tied to V through a pullup resistor whose  
CC  
2
minimum value is determined by the current sinking capability of  
the driver.  
3
NC  
GND  
D2  
4
5
LogicBlockDiagram  
6
NC  
VCC  
D3  
1
7
1OE  
8
9
NC  
D4  
28  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
2OE  
GND  
NC  
D5  
56-Pin  
A,K  
2
1Q1  
56  
CLK  
C1  
NC  
D6  
55  
3
D1  
1D  
1Q2  
NC  
D7  
GND  
NC  
D8  
TO 9 OTHER CHANNELS  
NC  
VCC  
D9  
PinDescription  
Pin Name  
Description  
NC  
GND  
D10  
NC  
NC  
OE  
Output Enable Input (Active LOW)  
Clock Input (Active HIGH)  
3-State Outputs  
Ax  
Yx  
GND  
VCC  
Ground  
Power  
PS8446A  
03/22/01  
1

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