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PI74AVC+16820K PDF预览

PI74AVC+16820K

更新时间: 2024-10-28 20:33:23
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
11页 265K
描述
Bus Driver, AVC Series, 1-Func, 10-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56

PI74AVC+16820K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP56,.25,16
针数:56Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.46Is Samacsys:N
系列:AVCJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:11.3 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:180000000 Hz最大I(ol):0.024 A
位数:10功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.25,16封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:2.7 ns
传播延迟(tpd):4 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mmBase Number Matches:1

PI74AVC+16820K 数据手册

 浏览型号PI74AVC+16820K的Datasheet PDF文件第2页浏览型号PI74AVC+16820K的Datasheet PDF文件第3页浏览型号PI74AVC+16820K的Datasheet PDF文件第4页浏览型号PI74AVC+16820K的Datasheet PDF文件第5页浏览型号PI74AVC+16820K的Datasheet PDF文件第6页浏览型号PI74AVC+16820K的Datasheet PDF文件第7页 
PI74AVC+16820  
2.5V 10-Bit Flip-Flop with  
Dual and 3-State Outputs  
Features  
Description  
• PI74AVC+16820 is designed for low-voltage operation,  
Pericom Semiconductor’s PI74AVC+16820, a 10-bit flip-flop  
V
= 1.65V to 3.6V  
designed for 1.65V to 3.6V V operation. It is designed with  
CC  
CC  
edge-triggeredD-typeip-ops. Onthepositivetransitionofclock  
(CLK) input. The device provides true data at the Q outputs.  
• True ±24mA Balanced Drive @ 3.3V  
• I supports Partial power-down operation  
OFF  
A buffered output-enable (OE) input can be used to place the ten  
outputs in either a normal logic state (HIGH or LOW level) or  
a high-impedance state. In the high-impedance state, the outputs  
neitherloadnordrivethebuslinessignificantly.Thehigh-impedance  
state and increased drive provide the capacity to drive bus lines  
without the need for interface or pullup components.  
• 3.6V I/O Tolerant inputs and outputs  
• All outputs contain a patented DDC (Dynamic Drive-  
Control) circuit that reduces noise without degrading  
propagation delay.  
• Industrial operation: –40°C to +85°C  
• Packaging (Pb-free & Green available):  
– 56-pin 240-mil wide plastic TSSOP (A)  
– 56-pin 173-mil wide plastic TVSOP (K)  
OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
To ensure the high-impedance state during power-up or power-  
down, OE should be tied to V through a pullup resistor whose  
CC  
minimum value is determined by the current sinking capability of  
the driver.  
Pin Configuration  
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Block Diagram  
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1
1OE  
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ꢅ  
28  
2OE  
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ꢍꢐ  
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2
1Q1  
56  
55  
CLK  
D1  
C1  
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3
1D  
1Q2  
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TO 9 OTHER CHANNELS  
PS8446D  
08/18/04  
1

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