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PI74AVC+16646AEX PDF预览

PI74AVC+16646AEX

更新时间: 2024-10-28 21:15:39
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
11页 376K
描述
Registered Bus Transceiver, 2-Func, 8-Bit, True Output, CMOS, PDSO56,

PI74AVC+16646AEX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP56,.3,20Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.73
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
负载电容(CL):30 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:3.3 V
Prop。Delay @ Nom-Sup:2 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
Base Number Matches:1

PI74AVC+16646AEX 数据手册

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PI74AVC+16646  
2.5V 16-Bit Bus Transceiver and  
Register with 3-State Outputs  
Product Features  
ProductDescription  
ThePI74AVC+16646isa16-bitbustransceiverandregisterdesigned  
for 1.65V to 3.6V VCC operation. It can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the A or B bus is  
clocked into the registers on the low-to-high transition of the  
appropriate Clock (CLKAB or CLKBA) input. Four fundamental  
bus-management functions can be performed.  
PI74AVC+16646 is designed for low-voltage operation,  
VCC = 1.65V to 3.6V  
True ±24mA Balanced Drive @ 3.3V  
IOFF supports partial power-down operation  
3.6V I/O Tolerant Inputs and Outputs  
OutputEnable(OE)andDirectionControl(DIR)inputsareprovided  
to control the transceiver functions. In the transceiver mode, data  
present at the high-impedance port may be stored in either register  
orinboth. TheSelectControl(SABandSBA)inputscanmultiplex  
stored and real-time (transparent mode) data. Circuitry used for  
Select Control eliminates the typical decoding glitch that occurs in  
a multiplexer during the transition between stored and real-time  
data. DIRdetermineswhichbusreceivesdatawhenOEisLOW. In  
theisolationmode(OEHIGH), Adatamaybestoredinoneregister  
and/or B data may be stored in the other register.  
All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
Industrial operation: –40°C to +85°C  
Packaging (Pb-free & Green available):  
– 56-pin 240 mil wide plastic TSSOP (A)  
When an output function is disabled, the input function is still  
enabled and may be used to store and transmit data. Only one of the  
two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor; the  
minimumvalueoftheresistorisdeterminedbythecurrent-sinking  
capability of the driver.  
Logic Block Diagrams  
56  
29  
1OE  
2OE  
1
28  
1DIR  
2DIR  
55  
30  
1CLKBA  
2CLKBA  
54  
31  
27  
1SBA  
2SBA  
2
1CLKAB  
2CLKAB  
3
1SAB  
26  
2SAB  
One of Eight Channels  
1D  
C1  
One of Eight Channels  
1D  
C1  
5
1A1  
15  
2A1  
52  
1B1  
42  
2B1  
1D  
C1  
1D  
C1  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
PS8506B  
06/01/06  
1
06-0170  

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