5秒后页面跳转
PI6C2510-133LE PDF预览

PI6C2510-133LE

更新时间: 2024-11-07 20:03:51
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
4页 273K
描述
PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, GREEN, TSSOP-24

PI6C2510-133LE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
系列:6C输入调节:STANDARD
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:SERIES-RESISTOR
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mm最小 fmax:150 MHz
Base Number Matches:1

PI6C2510-133LE 数据手册

 浏览型号PI6C2510-133LE的Datasheet PDF文件第2页浏览型号PI6C2510-133LE的Datasheet PDF文件第3页浏览型号PI6C2510-133LE的Datasheet PDF文件第4页 
PI6C2510-133  
Low-Noise, Phase-Locked Loop  
Clock Driver with 10 Clock Outputs  
Product Features  
Product Description  
Operating Frequency up to 150 MHz  
The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-  
locked loop (PLL) clock driver, distributing high-frequency clock  
signals for SDRAM and server applications. By connecting the  
feedback FB_OUT output to the feedback FB_IN input, the propa-  
gation delay from the CLK_IN input to any clock output will be  
nearly zero. This zero-delay feature allows the CLK_IN input  
clocktobedistributed, providingoneclockinputtoonebankoften  
outputs, with an output enable.  
Low-Noise Phase-Locked Loop Clock Distribution that  
meets 133 MHz Registered DIMM Synchronous DRAM  
modules for server/workstation/PC applications  
Allows Clock Input to have Spread Spectrum modulation  
for EMI reduction  
Zero Input-to-Output delay: Distribute one Clock Input  
to one Bank of Ten outputs, with an output enable.  
Low jitter: Cycle-to-Cycle jitter ±75ps max.  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
This clock driver is designed to meet the PC133 SDRAM Regis-  
tered DIMM specification. For test purposes, the PLL can be  
bypassed by strapping AV to ground.  
CC  
Operates at 3.3V V  
CC  
Package:Plastic24-pinTSSOP(L)  
Logic Block Diagram  
Product Pin Configuration  
24-Pin  
L
Functional Table  
Inputs  
Outputs  
G
L
Y[0:9]  
L
FB_OUT  
CLK_IN  
CLK_IN  
H
CLK_IN  
PS8383A  
07/26/99  
1

PI6C2510-133LE 替代型号

型号 品牌 替代类型 描述 数据表
CDCF2510PWR TI

类似代替

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWR TI

类似代替

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与PI6C2510-133LE相关器件

型号 品牌 获取价格 描述 数据表
PI6C2510-133LEX PERICOM

获取价格

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 M
PI6C2510-133LX PERICOM

获取价格

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-
PI6C2510A PERICOM

获取价格

Phase-Lock Loop Clock Driver with 10-Clock Outputs
PI6C2510AL PERICOM

获取价格

Phase-Lock Loop Clock Driver with 10-Clock Outputs
PI6C2510ALE PERICOM

获取价格

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.173
PI6C2516 PERICOM

获取价格

Phase-Locked Loop Clock Driver with 16 Clock Outputs
PI6C2516A PERICOM

获取价格

Phase-Locked Loop Clock Driver with 16 Clock Outputs
PI6C2516AX PERICOM

获取价格

PLL Based Clock Driver, 6C Series, 16 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-
PI6C2520 ETC

获取价格

Clock IC | 135 MHz. 20 Output Zero-Delay Clock Driver
PI6C2520A ETC

获取价格

Twenty Distributed-Output Clock Driver