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PI6C2510AL PDF预览

PI6C2510AL

更新时间: 2024-11-24 01:15:55
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
5页 335K
描述
Phase-Lock Loop Clock Driver with 10-Clock Outputs

PI6C2510AL 数据手册

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PI6C2510A  
Phase-Lock Loop Clock Driver  
with 10-Clock Outputs  
Description  
Features  
The PI6C2510A family is a low-skew, low-jitter, phase-lock loop  
(PLL) clock driver, distributing high-frequency clock signals for  
SDRAM and server applications. By connecting the feedback  
FB_OUT output to the feedback FB_IN input, the propagation  
delayfromtheCLK_INinputtoanyclockoutputwillbenearlyzero.  
This zero-delay feature allows the CLK_IN input clock to be  
distributed, providing one clock input to one bank of ten outputs,  
with an output enable.  
High-Performance Phase-Lock Loop Clock Distribution that  
meets 100/134 MHz Registered DIMM Synchronous DRAM  
modules for server/workstation/PC applications  
Allows Clock Input to have Spread Spectrum modulation for  
EMI reduction  
Zero Input-to-Output delay: Distribute One Clock Input  
to one bank of ten outputs, with an output enable.  
SamepinoutasTICDC2510/2510A  
The PI6C2510A is designed to meet PC100 SDRAM Registered  
DIMM Specification, for heavy load applications. For test pur-  
Lowjitter:Cycle-to-Cyclejitter±100psmax.  
poses, the PLL can be bypassed by strapping AV to ground.  
CC  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
The PI6C2510A family has the same pinouts as TI’s CDC2510A/  
2510B, withenhancedrise/falltimes, andallowing aSpreadSpec-  
trum clock input.  
Operatesat3.3VV  
CC  
Wide Clock Frequency Range:  
Packaging  
-24-pinTSSOP (L)  
Logic Block Diagram  
Product Pin Configuration  
CLK_IN  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
AGND  
AV  
V
1Y0  
CC  
CC  
V
G
CC  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
1Y5  
10  
1Y1  
1Y2  
GND  
GND  
1Y3  
1Y[0:9]  
24-Pin  
L
CLK_IN  
FB_OUT  
PLL  
FB_IN  
AV  
9
1Y4  
10  
11  
12  
V
CC  
G
CC  
V
CC  
FB_IN  
FB_OUT  
Functional Table  
Inputs  
Outputs  
G
X
L
CLK_IN  
1Y[0:9]  
FB_OUT  
L
H
H
L
L
H
L
H
H
H
08-0298  
PS8306C  
11/13/08  
1

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