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PI6C2520 PDF预览

PI6C2520

更新时间: 2024-11-06 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器
页数 文件大小 规格书
6页 284K
描述
Clock IC | 135 MHz. 20 Output Zero-Delay Clock Driver

PI6C2520 数据手册

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PI6C2520  
Low-Noise Phase-Locked Loop  
Clock Driver with 20 Clock Outputs  
Product Features  
Product Description  
• Low-Noise Phase-Locked Loop Clock Distribution.  
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL)  
clock driver, distributing low-noise clock signals for Networking  
Applications. By connecting the feedback FB_OUT output to the  
feedback FB_IN input, the propagation delay from the CLK_IN  
input to any clock output will be nearly zero. This zero-delay  
feature allows the CLK_IN input clock to be distributed, providing  
5 banks of 4 clocks and an extra clock for feedback.  
• Allows Clock Input to have Spread Spectrum modulation  
for EMI reduction. The clock outputs track the Clock Input  
modulation.  
• Maximumclockfrequencyof125MHz.  
• Zero Input-to-Output delay.  
• Low jitter: Cycle-to-Cycle jitter ±100ps max.  
• On-chip series damping resistor at clock output drivers for  
low noise and EMI reduction.  
For test purposes, the PLL can be bypassed by strapping AV to  
ground. The PI6C2520, which allows a Spread Spectrum clock in-  
CC  
put, operates at 3.3V V and provides integrated series-damping  
CC  
• Operates at 3.3V VCC  
• Output-to-Output skew less than 200ps.  
• Package: Plastic 56-pin TSSOP (A).  
.
resistors that make it ideal for driving point-to-point loads. Output  
signal duty cycles are adjusted to 50 percent, independent of the  
duty cycle at the input clock.  
Each bank of outputs can be enabled or disabled via the 1G, 2G,  
3G, 4G, and 5G control inputs. When the G inputs are high, the  
outputs switch in phase and frequency with CLK_IN. When the G  
inputs are low, the outputs are disabled to the logic low state.  
BlockDiagram  
ProductPinConfiguration  
1
V
V
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1G  
CC  
CC  
Y
4
2
Y
4 0  
Y
4 1  
GND  
GND  
1 0  
1Y [0:3]  
3
Y
1 1  
GND  
GND  
2G  
4
4
2Y [0:3]  
5
3G  
4
6
Y
4 2  
Y
4 3  
Y
3Y [0:3]  
1 2  
7
Y
1 3  
4G  
4
8
V
V
4Y [0:3]  
CC  
CC  
9
4G  
1G  
5G  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
AV  
GND  
AV  
CC  
CC  
4
FB_IN  
AGND  
FB_OUT  
GND  
CLK_IN  
CLK_IN  
FB_IN  
5Y [0:3]  
56-Pin  
A
AGND  
5G  
PLL  
FB_OUT  
GND  
2G  
AV  
CC  
3G  
V
V
CC  
CC  
Y
3 0  
Y
3 1  
GND  
GND  
Y
2 0  
Y
2 1  
GND  
GND  
Y
3 2  
Y
3 3  
Y
2 2  
Y
2 3  
V
V
CC  
CC  
V
V
CC  
CC  
Y
5 3  
Y
5 2  
GND  
Y
5 0  
Y
5 1  
GND  
PS8435B  
07/25/00  
1

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