PI6C2973
Low Voltage PLL Clock Driver
can be realized by pulsing low one clock edge prior to the
coincident edges of the Qa and Qc outputs. The Sync output will
indicate when the coincident rising edges of the above relation-
ships will occur. The Power–On Reset ensures proper program-
ming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output
and the other outputs. The internal power–on reset is designed
to provide this function, but with power–up conditions being
dependent, it is difficult to guarantee. All other conditions of the
fsel pins will automatically synchronize during PLL lock acquisi-
tion.
The PI6C2973 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2973 have internal
pull–up resistors.
ThePI6C2973isfully3.3Vcompatibleandrequiresnoexternal
loopfiltercomponents.AllinputsacceptLVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with
the capability to drive 50 Ohm transmission lines. For series
terminated lines each PI6C2973 output can drive two 50 Ohm
lines in parallel thus effectively doubling the fanout of the
device.
Features
• FullyIntegratedPLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3VV
CC
• + 100ps Typical Cycle–to–Cycle Jitter
• Packaging:
-52-pinLQFP
Description
ThePI6C2973are3.3Vcompatible,PLLbasedclockdriver
devices targeted for high-performance CISC or RISC processor
based systems. With output frequencies of up to 125 MHz and
skews of 550ps the PI6C2973 are ideally suited for most synchro-
nous systems. The devices offer twelve low skew outputs plus a
feedback and sync output for added flexibility and ease of
systemimplementation.
The PI6C2973 features an extensive level of frequency program-
mability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of
1:1,2:1,3:1,3:2,4:1,4:3,5:1,5:2,5:3,6:1and6:5betweenoutputs
PinConfiguration-PI6C2973
39 38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
fselFB1
QSync
GNDO
Qc0
fselb1
fselb0
fsela1
fsela0
Qa3
40
41
42
43
44
45
46
47
48
49
50
51
52
VCCO
Qc1
VCCO
Qa2
fselc0
fselc1
Qc2
GNDO
Qa1
VCCO
Qc3
VCCO
Qa0
GND0
Inv_Clk
GND0
VCO_Sel
1
2
3
4
5
6
7
8
9 10 11 12 13
PS8685
05/27/03
1