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PI6C2952-1FBEX PDF预览

PI6C2952-1FBEX

更新时间: 2024-11-23 19:19:31
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
6页 74K
描述
PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32

PI6C2952-1FBEX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
系列:6C输入调节:STANDARD
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:11
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.55 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
最小 fmax:180 MHzBase Number Matches:1

PI6C2952-1FBEX 数据手册

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PI6C2952  
Low Voltage PLL Clock Driver  
Features  
Description  
• ±100psCycle-to-CycleJitter  
• FullyIntegratedPLL  
ThePI6C2952isa3.3Vcompatible,PLL-basedclockdriverdevice  
targeted for high-performance clock applications. The device fea-  
tures a fully integrated PLL with no external components  
required. With output frequencies up to 180MHz and eleven low-  
skew outputs, the PI6C2952 is well suited for high-performance  
designs. The device employs a fully differential PLL design to  
optimize jitter and noise rejection performance.  
• Output Frequency up to 180MHz  
• High-Impedance Disabled Outputs  
• CompatiblewithPowerPC,Intel,andHigh-Performance  
RISC Microprocessors  
The PI6C2952 features three banks of individually configurable  
outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The  
internaldividecircuitryallowsforoutputfrequencyratiosof 1:1,2:1,  
3:1,and3:2:1.Theoutputfrequencyrelationshipiscontrolledbythe  
fsel frequency control pins. The fsel pins and other inputs are  
LVCMOS/LVTTLcompatibleinputs.  
• Configurable Output Frequency  
• 32-PinLQFPPackage(FB)  
PinConfiguration  
The PI6C2952 uses external feedback to the PLL. This features  
allows the device to be used as a “zero delay” buffer. Any of the  
elevenoutputscanbeusedasfeedbacktothePLL.TooptimizePLL  
stability and jitter performance,the VCO_Sel pin allows for the  
choice of two VCO ranges. For board level test, the MR/OE pin  
allows a user to force the outputs into high impedance. For system  
debug,thePI6C2952’sPLLcanbebypassed.Whenforcedtoalogic  
HIGH, the PL_LEN input routes the signal on the RefClk input  
around the PLL directly to the internal dividers. Because the signal  
is routed through the dividers, it may take several transitions of the  
RefClk to affect a transition on the outputs. This features allows a  
designer to single step the design for debug purposes.  
24 23 22 21 20 19 18 17  
16  
15  
14  
13  
12  
11  
10  
9
VCCO  
Qa2  
VCCO  
Qb2  
25  
26  
27  
28  
29  
30  
31  
32  
Qa1  
Qb3  
32-Pin  
FB  
GNDO  
Qa0  
GNDO  
GNDO  
Qc0  
VCCI  
VCCA  
PLL_En  
Qc1  
VCCO  
1
2
3
4
5
6 7 8  
ThePI6C2952’soutputsareLVCMOSwhichareoptimallydesigned  
todriveterminatedtransmissionlines.Forapplicationsusingseries-  
terminatedtransmissionlines,eachPI6C2952outputcandrivetwo  
lines. This capability provides an effective fanout of 22, more than  
enough clocks for most clock tree designs.  
PS8542A  
01/30-06  
1

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