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PI6C2972FB

更新时间： 2024-11-23 21:02:59
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
7页 167K
描述
PLL Based Clock Driver, 6C Series, 12 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52

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中文翻译

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PI6C2972FB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：52Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.91系列：6C
输入调节：MUXJESD-30 代码：S-PQFP-G52
JESD-609代码：e0长度：10 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：52
实输出次数：12最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.55 ns座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mm最小 fmax：200 MHz
Base Number Matches：1

PI6C2972FB 数据手册

 浏览型号PI6C2972FB的Datasheet PDF文件第2页浏览型号PI6C2972FB的Datasheet PDF文件第3页浏览型号PI6C2972FB的Datasheet PDF文件第4页浏览型号PI6C2972FB的Datasheet PDF文件第5页浏览型号PI6C2972FB的Datasheet PDF文件第6页浏览型号PI6C2972FB的Datasheet PDF文件第7页 
TARGET SPECIFICATION  
PI6C2972, PI6C2973  
Low Voltage PLL Clock Driver  
outputs can be realized by pulsing low one clock edge prior to  
the coincident edges of the Qa and Qc outputs. The Sync output  
will indicate when the coincident rising edges of the above  
relationships will occur. The Power–On Reset ensures proper  
programming if the frequency select pins are set at power up. If  
the fselFB2 pin is held high, it may be necessary to apply a reset  
after power–up to ensure synchronization between the QFB  
output and the other outputs. The internal power–on reset is  
designed to provide this function, but with power–up conditions  
being dependent, it is difficult to guarantee. All other conditions  
of the fsel pins will automatically synchronize during PLL lock  
acquisition.  
Features  
• FullyIntegratedPLL  
• Output Frequency up to 125 MHz  
• Compatible with PowerPC and Pentium Microprocessors  
• 3.3VV  
CC  
• + 100ps Typical Cycle–to–Cycle Jitter  
• Availablepackaging:52-pinLQFP  
Description  
ThePI6C2972/2973offersaveryflexibleoutputenable/disable  
scheme. Note that all of the control inputs on the PI6C2972/2973  
have internal pull–up resistors.  
ThePI6C2972/2973are3.3Vcompatible,PLLbasedclockdriver  
devices targeted for high-performance CISC or RISC processor  
based systems. With output frequencies of up to 125 MHz and  
skews of 550ps the PI6C2972/2973 are ideally suited for most  
synchronous systems. The devices offer twelve low skew  
outputs plus a feedback and sync output for added flexibility and  
ease of system implementation.  
ThePI6C2972/2973isfully3.3Vcompatibleandrequiresno  
external loop filter components. All inputs accept LVCMOS/  
LVTTLcompatiblelevelswhiletheoutputsprovideLVCMOS  
levels with the capability to drive 50 Ohm transmission lines. For  
series terminated lines each PI6C2972/2973 output can drive two  
50 Ohm lines in parallel thus effectively doubling the fanout of  
the device.  
The PI6C2972/2973 features an extensive level of frequency  
programmability between the 12 outputs as well as the input vs  
output relationships. Using the select lines output frequency  
ratiosof1:1,2:1,3:1,3:2,4:1,4:3,5:1,5:2,5:3,6:1and6:5between  
PinConfiguration-PI6C2972  
PinConfiguration-PI6C2973  
39 38 37 36 35 34 33 32 31 30 29 28 27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
fselFB1  
QSync  
GNDO  
Qc0  
fselb1  
fselb0  
fsela1  
fsela0  
Qa3  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
fselFB1  
QSync  
GNDO  
Qc0  
fselb1  
fselb0  
fsela1  
fsela0  
Qa3  
VCCO  
Qc1  
VCCO  
Qc1  
VCCO  
Qa2  
VCCO  
Qa2  
fselc0  
fselc1  
Qc2  
fselc0  
fselc1  
Qc2  
GNDO  
Qa1  
GNDO  
Qa1  
VCCO  
Qc3  
VCCO  
Qa0  
VCCO  
Qc3  
VCCO  
Qa0  
GND0  
Inv_Clk  
GND0  
VCO_Sel  
GND0  
Inv_Clk  
GND0  
VCO_Sel  
1
2
3
4
5
6
7
8
9 10 11 12 13  
PSXXXX  
07/14/00  
1
1234567

中文翻译

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