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PI6C2516

更新时间: 2024-11-06 22:44:27
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器
页数 文件大小 规格书
7页 300K
描述
Phase-Locked Loop Clock Driver with 16 Clock Outputs

PI6C2516 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
风险等级:5.88JESD-30 代码:R-PDSO-G48
JESD-609代码:e0最大I(ol):0.012 A
端子数量:48最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

PI6C2516 数据手册

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PI6C2516  
Phase-Locked Loop Clock Driver  
with 16 Clock Outputs  
Description  
Product Features  
The PI6C2516 family is a low-skew, low jitter, phase-locked loop  
(PLL) clock driver, distributing high-frequency clock signals for  
SDRAM, server and networking applications. By connecting the  
feedback FB_OUT output to the feedback FB_IN input, the propa-  
gation delay from the CLK input to any clock output will be nearly  
zero. This zero-delay feature allows the CLK input clock to be  
distributed, providing 4 banks of four outputs.  
• High Performance Phase-Locked Loop Clock Distribution for  
Synchronous DRAM, server and networking applications.  
• Zero Input-to-Output delay: Distribute One Clock Input  
to four banks of four outputs, with separate output enables  
for each bank.  
• Allow Clock Input to have Spread Spectrum modulation for  
EMI reduction. The clock outputs track the Clock Input  
modulation.  
For test purposes, the PLL can be bypassed by strapping the AV  
to ground.  
CC  
• Maximumclockfrequencyof150MHz.  
ThePI6C2516familyhasthesame pinoutas theTICDC2516,with  
the added feature of allowing Spread Spectrum clock input.  
• Lowjitter:Cycle-to-Cyclejitter ±100psmax  
• Operatesat3.3VV  
CC  
• AvailablePackaging:  
–48-pinTSSOP(ThinShrinkSmallOutline)(A)  
Pin Description  
Block Diagram  
V
1
CC  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
CC  
1Y0  
1Y1  
1G  
2
4Y0  
4Y1  
GND  
GND  
4Y2  
4Y3  
4
1Y [0:3]  
3
2G  
GND  
GND  
1Y2  
4
4
2Y [0:3]  
5
3G  
6
4
3Y [0:3]  
1Y3  
7
V
8
4G  
CC  
V
CC  
9
1G  
4G  
GND  
AV  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
AV  
CC  
CLK  
48-Pin  
A
4
CLK  
4Y [0:3]  
CC  
PLL  
FB_IN  
AGND  
FB_OUT  
GND  
FB_IN  
FB_OUT  
AGND  
AGND  
GND  
2G  
AV  
CC  
3G  
V
V
CC  
CC  
2Y0  
3Y0  
3Y1  
GND  
GND  
3Y2  
3Y3  
2Y1  
GND  
GND  
2Y2  
2Y3  
V
CC  
V
CC  
PS8440C  
07/24/01  
1

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