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PI6C2510-133E PDF预览

PI6C2510-133E

更新时间: 2024-11-07 06:03:11
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器
页数 文件大小 规格书
4页 332K
描述
Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

PI6C2510-133E 数据手册

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PI6C2510-133E  
Low-Noise, Phase-Locked Loop  
Clock Driver with 10 Clock Outputs  
Features  
Description  
• Operating Frequency up to 150 MHz  
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter,  
phase-locked loop (PLL) clock driver, distributing high-  
frequency clock signals for SDRAM and server applications. By  
connecting the feedback FB_OUT output to the feedback FB_IN  
input, the propagation delay from the CLK_IN input to any  
clock output will be nearly zero. This zero-delay feature allows  
the CLK_IN input clock to be distributed, providing one clock  
input to one bank of ten outputs, with an output enable.  
• Low-Noise Phase-Locked Loop Clock Distribution that  
meets 133 MHz Registered DIMM Synchronous DRAM mod-  
ules for server/workstation/PC applications  
• Allows Clock Input to have Spread Spectrum modulation  
for EMI reduction  
• Low jitter: Cycle-to-Cycle jitter ±75ps max.  
• On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
This clock driver is designed to meet the PC133 SDRAM  
Registered DIMM specication. For test purposes, the PLL can  
be bypassed by strapping AVCC to ground.  
• Operates at 3.3V VCC, 0–85°C  
• Packages (Pb-free & Green available):  
– Plastic 24-pin TSSOP (L)  
Block Diagram  
Pin Conguration  
G
AGND  
24 CLK_IN  
1
2
3
4
5
6
7
8
10  
V
23 AV  
CC  
Y0  
Y1  
CC  
Y[0:9]  
22  
V
CC  
21 Y9  
20 Y8  
19 GND  
18 GND  
17 Y7  
16 Y6  
15 Y5  
Y2  
CLK_IN  
24-Pin  
L
FB_OUT  
GND  
GND  
Y3  
PLL  
FB_IN  
Y4  
CC  
9
V
10  
11  
12  
AVcc  
G
14  
13 FB_IN  
V
CC  
FB_OUT  
Functional Table  
Inputs  
Outputs  
G
L
Y[0:9]  
L
FB_OUT  
CLK_IN  
CLK_IN  
H
CLK_IN  
PS8505B  
08/30/07  
07-0199  
1

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