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OMAP3503ECUSA

更新时间: 2024-02-12 19:43:56
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OMAP3503ECUSA 数据手册

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OMAP3515/03 Applications Processor  
www.ti.com  
SPRS505FEBRUARY 2008  
Table 1-1. Differences Between CBB and CUS Packages  
Feature  
Pin Assignments  
CBB Package  
CUS Package  
Pin assignments are different from the CUS  
package. For CUS package pin assignments, see  
Table 2-2, Ball Characteristics (CUS Package).  
For CBB package pin assignments, see Table 2-1,  
Ball Characteristics (CBB Package).  
Package-On-Package (POP)  
Interface  
POP interface supported.  
Eight chip select pins available.  
Four wait pins available.  
POP interface not available.  
Chip select pins gpmc_ncs1 and gpmc_ncs2 are  
not available.  
GPMC  
Wait pins gpmc_wait1 and gpmc_wait2 are not  
available.  
The following signals are available on two pins  
(double muxed): uart2_cts (AF6/AB26), uart2_rts  
(AE6/AB25), uart2_tx (AF5/AA25), and uart2_rx  
(AE5/AD25).  
The following signals are available on one pin  
only: uart2_cts (V6), uart2_rts (V5), uart2_tx  
(W4), and uart2_rx (V4).  
UART2  
The following signals are available on three pins  
(triple muxed): mcbsp3_dx (AF6/AB26/V21),  
mcbsp3_dr (AE6/AB25/U21), mcbsp3_clkx  
The following signals are available on two pins  
only (double muxed): mcbsp3_dx (V6/W18),  
mcbsp3_dr (V5/Y18), mcbsp3_clkx (W4/V18),  
McBSP3  
GP Timer  
McBSP4  
(AF5/AA25/W21), and mcbsp3_fsx (AE5/AD25/K26). and mcbsp3_fsx (V4/AA19).  
The following signals are available on three pins  
(triple muxed): gpt8_pwm_evt (N8/AD25/V3),  
gpt9_pwm_evt (T8/AB26/Y2), gpt10_pwm_evt  
(R8/AB25/Y3), and gpt11_pwm_evt (P8/AA25/Y4).  
The following signals are available on two pins  
only (double muxed): gpt8_pwm_evt (G4/M4),  
gpt9_pwm_evt (F4/N4), gpt10_pwm_evt (G5/N3),  
and gpt11_pwm_evt (F3/M5).  
The following signals are available on two pins  
(double muxed): mcbsp4_clkx (T8/AE1), mcbsp4_dr  
(R8/AD1), mcbsp4_dx (P8/AD2), and mcbsp4_fsx  
(N8/AC1).  
The following signals are available on one pin  
only: mcbsp4_clkx (F4), mcbsp4_dr (G5),  
mcbsp4_dx (F3), and mcbsp4_fsx (G4).  
HSUSB3_TLL  
MM_FSUSB3  
Supported.  
Supported.  
Not Supported.  
Not Supported.  
Chip select pins mcspi1_cs1 and mcspi1_cs2 are  
not available.  
McSPI1  
Four chip select pins are available.  
The following signals are available on two pins  
(double muxed): mmc3_cmd (AC3/AE10) and  
mmc3_clk (AB1/AF10).  
The following signals are available on one pin  
only: mmc3_cmd (AD3) and mmc3_clk (AC1).  
MMC3  
A maximum of 170 GPIO pins are supported.  
The following GPIO pins are not available:  
gpio_112, gpio_113, gpio_114, gpio_115,  
gpio_52, gpio_53, gpio_63, gpio_64, gpio_144,  
gpio_145, gpio_146, gpio_147, gpio_152,  
gpio_153, gpio_154, gpio_155, gpio_175, and  
gpio_176.  
GPIO  
PLL  
A maximum of 188 GPIO pins are supported.  
The adpllv2d_dithering_en2 pin is supported.  
Pin muxing restricts the total number of GPIO  
pins available at one time. For more details, see  
Table 2-4, Multiplexing Characteristics (CUS  
Pkg.).  
The adpllv2d_dithering_en2 pin is not supported.  
This OMAP3515/03 Applications Processor data manual presents the electrical and mechanical  
specifications for the OMAP3515/03 Applications Processor. It consists of the following sections:  
A description of the OMAP3515/03 terminals: assignment, electrical characteristics, multiplexing, and  
functional description (Section 2)  
A presentation of the electrical characteristics requirements: power domains, operating conditions,  
power consumption, and dc characteristics (Section 3)  
The clock specifications: input and output clocks, DPLL and DLL (Section 4)  
The video DAC specification (Section 5)  
The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6)  
A description of thermal characteristics, device nomenclature, and mechanical data about the available  
packaging (Section 7)  
4
OMAP3515/03 Applications Processor  
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OMAP3503ECUSA 替代型号

型号 品牌 替代类型 描述 数据表
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完全替代

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OMAP3515ECUSA TI

完全替代

暂无描述
OMAP3503ECUS TI

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