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OMAP3525DCBB PDF预览

OMAP3525DCBB

更新时间： 2024-01-08 18:12:24
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
264页 3514K
描述
OMAP3530/25 Applications Processor: OMAP 3 Architecture

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OMAP3525DCBB 技术参数

是否Rohs认证： 符合生命周期：Lifetime Buy
零件包装代码：BGA包装说明：VFBGA, BGA515,26X26,20
针数：515Reach Compliance Code：compliant
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
风险等级：5.77地址总线宽度：26
边界扫描：YES最大时钟频率：38.4 MHz
外部数据总线宽度：16格式：FLOATING POINT
集成缓存：YESJESD-30 代码：S-PBGA-B515
JESD-609代码：e1长度：14 mm
低功率模式：YES湿度敏感等级：3
DMA 通道数量：32端子数量：515
片上数据RAM宽度：8最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA515,26X26,20
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.1,1.2,1.8,1.8/3 V
认证状态：Not QualifiedRAM（字数）：65536
座面最大高度：0.95 mm速度：600 MHz
子类别：Graphics Processors最大供电电压：1.35 V
最小供电电压：0.985 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

OMAP3525DCBB 数据手册

 浏览型号OMAP3525DCBB的Datasheet PDF文件第2页浏览型号OMAP3525DCBB的Datasheet PDF文件第3页浏览型号OMAP3525DCBB的Datasheet PDF文件第4页浏览型号OMAP3525DCBB的Datasheet PDF文件第5页浏览型号OMAP3525DCBB的Datasheet PDF文件第6页浏览型号OMAP3525DCBB的Datasheet PDF文件第7页 
OMAP3530/25 Applications Processor  
www.ti.com  
SPRS507F–FEBRUARY 2008–REVISED OCTOBER 2009  
1 OMAP3530/25 Applications Processor  
1.1 Features  
–
Additional C64x+™ Enhancements  
•
OMAP3530/25 Applications Processor:  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
–
–
OMAP™ 3 Architecture  
MPU Subsystem  
•
•
Up to 720-MHz ARM Cortex™-A8 Core  
NEON™ SIMD Coprocessor  
•
Hardware Support for Modulo Loop  
Operation  
–
–
High Performance Image, Video, Audio  
(IVA2.2™) Accelerator Subsystem  
•
C64x+ L1/L2 Memory Architecture  
–
–
–
–
32K-Byte L1P Program RAM/Cache (Direct  
Mapped)  
80K-Byte L1D Data RAM/Cache (2-Way  
Set-Associative)  
64K-Byte L2 Unified Mapped RAM/Cache  
(4-Way Set-Associative)  
32K-Byte L2 Shared SRAM and 16K-Byte L2  
ROM  
•
Up to 520-MHz TMS320C64x+™ DSP  
Core  
•
Enhanced Direct Memory Access  
(EDMA) Controller (128 Independent  
Channels)  
•
Video Hardware Accelerators  
POWERVR SGX™ Graphics Accelerator  
(OMAP3530 Device Only)  
•
C64x+ Instruction Set Features  
•
Tile Based Architecture Delivering up to  
10 MPoly/sec  
Universal Scalable Shader Engine:  
Multi-threaded Engine Incorporating  
Pixel and Vertex Shader Functionality  
Industry Standard API Support:  
OpenGLES 1.1 and 2.0, OpenVG1.0  
Fine Grained Task Switching, Load  
Balancing, and Power Management  
Programmable High Quality Image  
Anti-Aliasing  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation. Bit-Counting  
Compact 16-Bit Instructions  
Additional Instructions to Support Complex  
Multiplies  
•
•
•
•
•
ARM Cortex™-A8 Core  
–
ARMv7 Architecture  
•
•
•
Trust Zone®  
Thumb®-2  
MMU Enhancements  
–
–
Fully Software-Compatible With C64x and  
ARM9™  
Commercial and Extended Temperature  
Grades  
–
In-Order, Dual-Issue, Superscalar  
Microprocessor Core  
•
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
–
–
–
NEON™ Multimedia Architecture  
Over 2x Performance of ARMv6 SIMD  
Supports Both Integer and Floating Point  
SIMD  
–
Eight Highly Independent Functional Units  
•
+Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
–
Jazelle® RCT Execution Environment  
Architecture  
Dynamic Branch Prediction with Branch  
Target Address Cache, Global History  
Buffer, and 8-Entry Return Stack  
•
–
Embedded Trace Macrocell (ETM) Support  
for Non-Invasive Debug  
–
Load-Store Architecture With Non-Aligned  
Support  
–
–
–
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
•
ARM Cortex™-A8 Memory Architecture:  
–
16K-Byte Instruction Cache (4-Way  
Set-Associative)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
POWERVR SGX is a trademark of Imagination Technologies Ltd.  
OMAP is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2009, Texas Instruments Incorporated  
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