Datasheet > NSBMC096-16

NSBMC096-16

更新时间： 2024-01-01 06:27:51

品牌	Logo	应用领域
美国国家半导体 - NSC		内存控制器
页数	文件大小	规格书
18页	268K
描述
NSBMC096-16/-25/-33 Burst Memory Controller

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NSBMC096-16 数据手册

August 1993

NSBMC096-16/-25/-33 Burst Memory Controller

General Description

The NSBMC096 Burst Memory Controller is an integrated

The NSBMC096 has been designed to allow maximum flexi-

bility in its application. The full range of processor speeds is

supported for a wide range of DRAM speeds, sizes and or-

ganizations.

circuit which implements all aspects of DRAM control for

CA/CF

high performance systems using an i960

SuperScalar Embedded Processor. The NSBMC096 is func-

tionally equivalent to the V96BMC^TM

No glue logic is required because the bus interface is cus-

tomized to the i960 CA/CF. System integration is further

enhanced by providing a 24-bit heartbeat timer and a bus

watch timer on-chip.

The extremely high instruction rate achieved by these proc-

essors place extraordinary demands on memory system de-

sign if maximum throughput is to be sustained and costs

minimized.

The NSBMC096 is packaged as a 132-pin PQFP with a foot-

print of only 1.3 square inches. It reduces design complexi-

ty, space requirements and is fully derated for loading, tem-

perature and voltage.

Static RAM offers a simple solution for high speed memory

systems. However, high cost and low density make this an

expensive and space consumptive choice.

Dynamic RAMs are an attractive alternative with higher den-

sity and low cost. Their drawbacks are, slower access time

and more complex control circuitry required to operate

them.

Features

Interfaces directly to the i960 CA

Integrated Page Cache Management

The access time problem is solved if DRAMs are used in

page mode. In this mode, access times rival that of static

RAM. The control circuit problem is resolved by the

NSBMC096.

Manages Page Mode Dynamic Memory devices

On-chip Memory Address Multiplexer/Drivers

Supports DRAMs trom 256 kB to 64 MB

Bit counter/timer

The function that the NSBMC096 performs is to optimally

translate the burst access protocol of the i960 CA/CF to the

page mode access protocol supported by dynamic RAMs.

Non-interleaved or two way interleaved operation

5-Bit Bus Watch Timer

Software-configured operational parameters

The device manages one or two-way interleaved arrange-

ments of DRAMs such that during burst access, data can be

read, or written, at the rate of one word per system clock

cycle.

High-Speed/Low Power CMOS technology

Block Diagram

TL/V/11805–1

This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information

is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications

of this product without notice.

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

NSBMC096^TMand WATCHDOG^TMare trademarks of National Semiconductor Corporation.

i960É is a registered trademark of Intel Corporation.

V96BMC^TMis a trademark of V3 Corporation.

1995 National Semiconductor Corporation

TL/V/11805

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7...18

中文翻译

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与NSBMC096-16相关器件

型号	品牌	获取价格	描述	数据表
NSBMC096VF	NSC	获取价格	NSBMC096-16/-25/-33 Burst Memory Controller
NSBMC096VF16	NSC	获取价格	IC 16M X 1, DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132, Memory Controller
NSBMC096VF-16	ETC	获取价格	DRAM Controller
NSBMC096VF25	NSC	获取价格	IC 16M X 1, DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132, Memory Controller
NSBMC096VF25	TI	获取价格	16MX1, DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132
NSBMC096VF-25	ETC	获取价格	DRAM Controller
NSBMC096VF30	NSC	获取价格	IC 64M X 1, DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132, Memory Controller
NSBMC096VF-33	ETC	获取价格	DRAM Controller
NSBMC096VF-33C	NSC	获取价格	IC,MEMORY CONTROLLER,CMOS,QFP,132PIN
NSBMC290	ETC	获取价格

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