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NSBMC290VF-16 PDF预览

NSBMC290VF-16

更新时间: 2024-11-15 20:12:23
品牌 Logo 应用领域
美国国家半导体 - NSC 动态存储器外围集成电路
页数 文件大小 规格书
20页 317K
描述
IC DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132, Memory Controller

NSBMC290VF-16 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:BQFP, SPQFP132,1.1SQReach Compliance Code:unknown
风险等级:5.82地址总线宽度:32
边界扫描:NO外部数据总线宽度:
JESD-30 代码:S-PQFP-G132JESD-609代码:e0
长度:24.13 mm低功率模式:NO
区块数量:2端子数量:132
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BQFP
封装等效代码:SPQFP132,1.1SQ封装形状:SQUARE
封装形式:FLATPACK, BUMPER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:4.45 mm子类别:Memory Controllers
最大压摆率:100 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.64 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.13 mmuPs/uCs/外围集成电路类型:MEMORY CONTROLLER, DRAM
Base Number Matches:1

NSBMC290VF-16 数据手册

 浏览型号NSBMC290VF-16的Datasheet PDF文件第2页浏览型号NSBMC290VF-16的Datasheet PDF文件第3页浏览型号NSBMC290VF-16的Datasheet PDF文件第4页浏览型号NSBMC290VF-16的Datasheet PDF文件第5页浏览型号NSBMC290VF-16的Datasheet PDF文件第6页浏览型号NSBMC290VF-16的Datasheet PDF文件第7页 
July 1993  
NSBMC290TM-16/-20/-25/-33  
Burst Mode Memory Controller  
General Description  
The NSBMC290 is functionally equivalent to the  
V29BMCTM. The NSBMC290 Burst Mode Memory Control-  
ler is a single chip device designed to simplify the imple-  
mentation of burst mode access in high performance sys-  
tems using the Am29000TM Streamlined Instruction Proces-  
sor.  
The function of NSBMC290 is to interface the page mode  
access protocol of dynamic RAMs with the more general  
burst mode access protocol supported by the Am29000 lo-  
cal channel. The device manages a double banked arrang-  
ment of dynamic RAMs such that when burst accesses are  
permitted data can be read, or written, at the rate of one  
word per system clock cycle.  
The extremely high instruction rate achieved by this proces-  
sor places extraordinary demands on memory system de-  
signs if maximum throughput is to be sustained and costs  
minimized.  
Packaged as a 124 pin PGA or 132 pin PQFP, the  
NSBMC290 drives memory arrays directly, thus minimizing  
design complexity and package count.  
The most obvious solution to the problem of access speed  
is to implement system memory using high-speed static  
memories. However, the high cost and low density of these  
devices make them an expensive and space consumptive  
solution.  
Features  
Y
Interfaces directly to Am29000 Local Channel  
Y
Manages Page Mode Dynamic Memory devices  
Y
Supports DRAMs from 64 KB to 16 MB  
A more cost effective method of solving this problem is via  
the use of dynamic RAMs. Their high density and low cost  
make their use extremely attractive. The impediment to their  
use is their relatively slow access times.  
Y
Manages Instruction and/or Data Memory  
Y
Very Low Power Consumption  
Y
On-Chip Memory Address Multiplexer/Drivers  
Y
Flexible Instruction/Data Bus Buffer Management  
However when operated in page mode, dynamic RAMs be-  
have more like static memories. Properly managed, they  
can yield access times approaching those of fully static  
RAMs.  
Y
Software-Configured operational parameters  
Y
Auto-Configured Bank Size and Location  
Y
High-Speed CMOS Technology  
Block Diagram  
Logic Symbol  
Typical System Configuration  
TL/V/11803–2  
TL/V/11803–1  
This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information  
is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications  
of this product without notice.  
TRI-STATEÉ is a registered trademark National Semiconductor Corporation.  
NSBMC290TM is a trademark of National Semiconductor Corporation.  
V29BMCTM is a trademark of V3 Corporation.  
Am29000TM is a trademark of Advanced Micro Devices, Sunnyvale, California, USA.  
C
1995 National Semiconductor Corporation  
TL/V/11803  
RRD-B30M115/Printed in U. S. A.  

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