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NSBMC096VF-33C PDF预览

NSBMC096VF-33C

更新时间： 2024-11-15 21:13:27
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
18页 264K
描述
IC,MEMORY CONTROLLER,CMOS,QFP,132PIN

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NSBMC096VF-33C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：BQFP, SPQFP132,1.1SQReach Compliance Code：unknown
风险等级：5.92JESD-30 代码：S-PQFP-G132
JESD-609代码：e0端子数量：132
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BQFP
封装等效代码：SPQFP132,1.1SQ封装形状：SQUARE
封装形式：FLATPACK电源：5 V
认证状态：Not Qualified子类别：Memory Controllers
最大压摆率：100 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

NSBMC096VF-33C 数据手册

 浏览型号NSBMC096VF-33C的Datasheet PDF文件第2页浏览型号NSBMC096VF-33C的Datasheet PDF文件第3页浏览型号NSBMC096VF-33C的Datasheet PDF文件第4页浏览型号NSBMC096VF-33C的Datasheet PDF文件第5页浏览型号NSBMC096VF-33C的Datasheet PDF文件第6页浏览型号NSBMC096VF-33C的Datasheet PDF文件第7页 
August 1993  
NSBMC096-16/-25/-33 Burst Memory Controller  
General Description  
The NSBMC096 Burst Memory Controller is an integrated  
The NSBMC096 has been designed to allow maximum flexi-  
bility in its application. The full range of processor speeds is  
supported for a wide range of DRAM speeds, sizes and or-  
ganizations.  
circuit which implements all aspects of DRAM control for  
CA/CF  
high performance systems using an i960  
É
SuperScalar Embedded Processor. The NSBMC096 is func-  
tionally equivalent to the V96BMCTM  
.
No glue logic is required because the bus interface is cus-  
tomized to the i960 CA/CF. System integration is further  
enhanced by providing a 24-bit heartbeat timer and a bus  
watch timer on-chip.  
The extremely high instruction rate achieved by these proc-  
essors place extraordinary demands on memory system de-  
sign if maximum throughput is to be sustained and costs  
minimized.  
The NSBMC096 is packaged as a 132-pin PQFP with a foot-  
print of only 1.3 square inches. It reduces design complexi-  
ty, space requirements and is fully derated for loading, tem-  
perature and voltage.  
Static RAM offers a simple solution for high speed memory  
systems. However, high cost and low density make this an  
expensive and space consumptive choice.  
Dynamic RAMs are an attractive alternative with higher den-  
sity and low cost. Their drawbacks are, slower access time  
and more complex control circuitry required to operate  
them.  
Features  
Y
Interfaces directly to the i960 CA  
Y
Integrated Page Cache Management  
Y
The access time problem is solved if DRAMs are used in  
page mode. In this mode, access times rival that of static  
RAM. The control circuit problem is resolved by the  
NSBMC096.  
Manages Page Mode Dynamic Memory devices  
Y
On-chip Memory Address Multiplexer/Drivers  
Y
Supports DRAMs trom 256 kB to 64 MB  
Y
Bit counter/timer  
The function that the NSBMC096 performs is to optimally  
translate the burst access protocol of the i960 CA/CF to the  
page mode access protocol supported by dynamic RAMs.  
Y
Non-interleaved or two way interleaved operation  
Y
5-Bit Bus Watch Timer  
Y
Software-configured operational parameters  
The device manages one or two-way interleaved arrange-  
ments of DRAMs such that during burst access, data can be  
read, or written, at the rate of one word per system clock  
cycle.  
Y
High-Speed/Low Power CMOS technology  
Block Diagram  
TL/V/11805–1  
This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information  
is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications  
of this product without notice.  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
NSBMC096TM and WATCHDOGTM are trademarks of National Semiconductor Corporation.  
i960É is a registered trademark of Intel Corporation.  
V96BMCTM is a trademark of V3 Corporation.  
C
1995 National Semiconductor Corporation  
TL/V/11805  
RRD-B30M115/Printed in U. S. A.  
1234567...18

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