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NSBMC290

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NSBMC290 数据手册

July 1993

NSBMC290^TM-16/-20/-25/-33

Burst Mode Memory Controller

General Description

The NSBMC290 is functionally equivalent to the

V29BMC^TM. The NSBMC290 Burst Mode Memory Control-

ler is a single chip device designed to simplify the imple-

mentation of burst mode access in high performance sys-

tems using the Am29000^TMStreamlined Instruction Proces-

sor.

The function of NSBMC290 is to interface the page mode

access protocol of dynamic RAMs with the more general

burst mode access protocol supported by the Am29000 lo-

cal channel. The device manages a double banked arrang-

ment of dynamic RAMs such that when burst accesses are

permitted data can be read, or written, at the rate of one

word per system clock cycle.

The extremely high instruction rate achieved by this proces-

sor places extraordinary demands on memory system de-

signs if maximum throughput is to be sustained and costs

minimized.

Packaged as a 124 pin PGA or 132 pin PQFP, the

NSBMC290 drives memory arrays directly, thus minimizing

design complexity and package count.

The most obvious solution to the problem of access speed

is to implement system memory using high-speed static

memories. However, the high cost and low density of these

devices make them an expensive and space consumptive

solution.

Features

Interfaces directly to Am29000 Local Channel

Manages Page Mode Dynamic Memory devices

Supports DRAMs from 64 KB to 16 MB

A more cost effective method of solving this problem is via

the use of dynamic RAMs. Their high density and low cost

make their use extremely attractive. The impediment to their

use is their relatively slow access times.

Manages Instruction and/or Data Memory

Very Low Power Consumption

On-Chip Memory Address Multiplexer/Drivers

Flexible Instruction/Data Bus Buffer Management

However when operated in page mode, dynamic RAMs be-

have more like static memories. Properly managed, they

can yield access times approaching those of fully static

RAMs.

Software-Configured operational parameters

Auto-Configured Bank Size and Location

High-Speed CMOS Technology

Block Diagram

Logic Symbol

Typical System Configuration

TL/V/11803–2

TL/V/11803–1

This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information

is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications

of this product without notice.

TRI-STATEÉ is a registered trademark National Semiconductor Corporation.

NSBMC290^TMis a trademark of National Semiconductor Corporation.

V29BMC^TMis a trademark of V3 Corporation.

Am29000^TMis a trademark of Advanced Micro Devices, Sunnyvale, California, USA.

1995 National Semiconductor Corporation

TL/V/11803

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7...20

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与NSBMC290相关器件

型号	品牌	获取价格	描述	数据表
NSBMC290-16	NSC	获取价格	Burst Mode Memory Controller
NSBMC290UP	NSC	获取价格	Burst Mode Memory Controller
NSBMC290UP-16	ETC	获取价格	DRAM Controller
NSBMC290UP-20	ETC	获取价格	DRAM Controller
NSBMC290UP-25	ETC	获取价格	DRAM Controller
NSBMC290UP-33	ETC	获取价格	DRAM Controller
NSBMC290VF	NSC	获取价格	Burst Mode Memory Controller
NSBMC290VF-16	NSC	获取价格	IC DRAM CONTROLLER, PQFP132, PLASTIC, QFP-132, Memory Controller
NSBMC290VF-20	ETC	获取价格	DRAM Controller
NSBMC290VF-25	ETC	获取价格	DRAM Controller

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